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| motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee r egarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters which may be provided in motorola data sheets and/or speci fications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each custom er application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intende d, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applica tion in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such uninte nded or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against al l claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unautho rized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. document number 9S12B128DGV1/d 1 ?motorola, inc., 2001 mc9s12b128 device user guide v01.10 covers also preliminary mc9s12b64 using mc9s12b128 die original release date: 22 nov 2002 revised: 17 mar 2004 semiconductor products sector motorola, inc. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee r egarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters which may be provided in motorola data sheets and/or speci fications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each custom er application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intende d, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applica tion in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such uninte nded or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against al l claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unautho rized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. document number 9S12B128DGV1/d 2 ?motorola, inc., 2001 revision history version number revision date effective date author description of changes v01.00 20 nov 2002 20 nov 2002 initial version based on mc9s12dgj64-1.10 version. v01.01 27 jan 2003 01 feb 2003 updated table 0-1; added submodule con?guration in section 6 & section 11. updated memory map $0118-$011b v01.02 24 feb 2003 24 feb 2003 updated table 0-1; updated section 2.2.28; updated memory map $0101. v01.03 18mar 2003 18 mar 2003 added the iic to the document; added for b64 more details in the preface and the according memory map out of reset v01.04 05may 2003 05 may 2003 updated bus frequency in table a-4 ; updated numbers in a.3.1.2 and a.3.1.3 v01.05 20 jun 2003 20 jun 2003 updated b64 details. corrected numbering in table a-26 . replaced references to hcs12 core guide by the individual hcs12 block guides. table 2-1 corrected pullrresistor reset state pe4-pe2. table a-1 corrected footnote on clamp of test pin. v01.06 01 sep 2003 01 sep 2003 updated section 11 , section 15 , a.5.2 oscillator table a-15 corrected num 9 and 10. v01.07 31 oct 2003 31 oct 2003 added table 0-2 and note at section 8.1 v01.08 22 jan 2004 22 jan 2004 updated table 1-3 v01.09 24 feb 2004 24 feb 2004 updated table 0-4 , row 6 of table a-15 v01.10 17 mar 2004 17 mar 2004 added table 0-3 , updated figure 0-1 and table 1-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 3 table of contents section 1 introduction 1.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5 system memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.5.1 detailed register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.6 part id assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 section 2 signal description 2.1 system pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 2.1.1 signal properties summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 2.2 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 2.2.1 extal, xtal oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 2.2.2 reset external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.2.3 test test pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.2.4 vregen voltage regulator enable pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.2.5 xfc pll loop filter pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.2.6 bkgd / taghi / modc background debug, tag high, and mode pin . . . . . . . .52 2.2.7 pad[15:0] / an[15:0] port ad input pins atd . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.2.8 pa[7:0] / addr[15:8] / data[15:8] port a i/o pins . . . . . . . . . . . . . . . . . . . . . . .53 2.2.9 pb[7:0] / addr[7:0] / data[7:0] port b i/o pins . . . . . . . . . . . . . . . . . . . . . . . . .53 2.2.10 pe7 / noacc / xclks port e i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.2.11 pe6 / modb / ipipe1 port e i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.12 pe5 / moda / ipipe0 port e i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.13 pe4 / eclk port e i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.14 pe3 / lstrb / taglo port e i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.15 pe2 / r/w port e i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.16 pe1 / irq port e input pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.17 pe0 / xirq port e input pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.18 ph7 / kwh7 port h i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.19 ph6 / kwh6 port h i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.20 ph5 / kwh5 port h i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 4 2.2.21 ph4 / kwh4 port h i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.22 ph3 / kwh3 port h i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.23 ph2 / kwh2 port h i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.24 ph1 / kwh1 port h i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.25 ph0 / kwh0 port h i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.26 pj7 / kwj7 / scl port j i/o pins 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.27 pj6 / kwj6 / sda port j i/o pins 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.28 pj[1:0] / kwj[1:0] port j i/o pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.29 pk7 / ecs / romctl port k i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.30 pk[5:0] / xaddr[19:14] port k i/o pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.31 pm7 port m i/o pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.32 pm6 port m i/o pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.33 pm5 / sck0 port m i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.34 pm4 / mosi0 port m i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.35 pm3 / ss0 port m i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.36 pm2 / miso0 port m i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.37 pm1 / txcan0 port m i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.38 pm0 / rxcan0 port m i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.39 pp7 / kwp7 / pwm7 port p i/o pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.40 pp6 / kwp6 / pwm6 port p i/o pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.41 pp5 / kwp5 / pwm5 port p i/o pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.42 pp4 / kwp4 / pwm4 port p i/o pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.43 pp3 / kwp3 / pwm3 port p i/o pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.44 pp2 / kwp2 / pwm2 port p i/o pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.45 pp1 / kwp1 / pwm1 port p i/o pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.46 pp0 / kwp0 / pwm0 port p i/o pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.47 ps7 / ss0 port s i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.48 ps6 / sck0 port s i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.49 ps5 / mosi0 port s i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.50 ps4 / miso0 port s i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.51 ps3 / txd1 port s i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.52 ps2 / rxd1 port s i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.53 ps1 / txd0 port s i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.54 ps0 / rxd0 port s i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.55 pt[7:0] / ioc[7:0] port t i/o pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 5 2.3.1 vddx, vssx power & ground pins for i/o drivers . . . . . . . . . . . . . . . . . . . . . . .60 2.3.2 vddr, vssr power & ground pins for i/o drivers & for internal voltage regulator 60 2.3.3 vdd1, vdd2, vss1, vss2 internal logic power supply pins . . . . . . . . . . . . . . .61 2.3.4 vdda, vssa power supply pins for atd and vreg . . . . . . . . . . . . . . . . . . . . .61 2.3.5 vrh, vrl atd reference voltage input pins . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.6 vddpll, vsspll power supply pins for pll . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.7 vregen on chip voltage regulator enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 section 3 system clock description section 4 modes of operation 4.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 4.2 chip configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 4.3 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.3.1 securing the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.3.2 operation of the secured microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.3.3 unsecuring the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 4.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 4.4.1 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 4.4.2 pseudo stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.3 wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 4.4.4 run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 section 5 resets and interrupts 5.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 5.2 vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 5.2.1 vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 5.3 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 5.3.1 i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 5.3.2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 5.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 section 6 hcs12 core block description 6.1 cpu12 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 6.1.1 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 6.2 hcs12 module mapping control (mmc) block description . . . . . . . . . . . . . . . . . . . . . .70 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 6 6.2.1 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 6.3 hcs12 multiplexed external bus interface (mebi) block description . . . . . . . . . . . . . .70 6.3.1 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 6.4 hcs12 interrupt (int) block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 6.5 hcs12 background debug (bdm) block description . . . . . . . . . . . . . . . . . . . . . . . . . .71 6.5.1 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 6.6 hcs12 breakpoint (bkp) block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 section 7 voltage regulator (vreg3v3) block description section 8 clock and reset generator (crg) block description 8.1 device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 section 9 oscillator (osc) block description 9.1 device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 section 10 standard timer (tim) block description section 11 analog to digital converter (atd) block description section 12 inter-ic bus (iic) block description section 13 serial communications interface (sci) block description section 14 serial peripheral interface (spi) block description section 15 flash eeprom 128k1 block description section 16 eeprom 1k block description section 17 ram block description section 18 mscan block description section 19 pulse width modulator (pwm) block description section 20 port integration module (pim) block description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 7 section 21 printed circuit board layout proposals appendix a electrical characteristics a.1 general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 a.1.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 a.1.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 0 a.1.3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 a.1.4 current injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 a.1.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 a.1.6 esd protection and latch-up immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 a.1.7 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 a.1.8 power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 a.1.9 i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 6 a.1.10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 8 a.2 atd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1 a.2.1 atd operating characteristics in 5v range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 a.2.2 atd operating characteristics in 3.3v range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 a.2.3 factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 a.2.4 atd accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4 a.3 nvm, flash and eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 a.3.1 nvm timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 a.3.2 nvm reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 a.4 vreg_3v3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 01 a.4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 a.4.2 chip power-up and voltage drops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 a.4.3 output loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2 a.5 reset, oscillator and pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 a.5.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 a.5.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 a.5.3 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 a.6 mscan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 a.7 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 a.7.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 a.7.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 7 a.8 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 a.8.1 general muxed bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 8 appendix b package information b.1 general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 b.2 112-pin lqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 b.3 80-pin qfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 9 list of figures figure 0-1 order partnumber example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 1-1 mc9s12b128 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 1-2 mc9s12b128 memory map out of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 1-3 mc9s12b64 using mc9s12b128 die memory map out of reset . . . . . . . . . . . .28 figure 2-1 pin assignments in 112-pin lqfp for mc9s12b128 . . . . . . . . . . . . . . . . . . . . .48 figure 2-2 pin assignments in 80-pin qfp for mc9s12b128 . . . . . . . . . . . . . . . . . . . . . . .49 figure 2-3 pll loop filter connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 2-4 colpitts oscillator connections (pe7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 2-5 pierce oscillator connections (pe7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 2-6 external clock connections (pe7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 3-1 clock connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 21-1 recommended pcb layout 112lqfp colpitts oscillator. . . . . . . . . . . . . . . . . .75 figure 21-2 recommended pcb layout for 80qfp colpitts oscillator . . . . . . . . . . . . . . . . .76 figure 21-3 recommended pcb layout for 112lqfp pierce oscillator . . . . . . . . . . . . . . . .77 figure 21-4 recommended pcb layout for 80qfp pierce oscillator . . . . . . . . . . . . . . . . . .78 figure a-1 atd accuracy definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure a-2 vreg_3v3 - chip power-up and voltage drops (not scaled). . . . . . . . . . . . . 102 figure a-3 basic pll functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure a-4 jitter definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure a-5 maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure a-6 spi master timing (cpha=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure a-7 spi master timing (cpha=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure a-8 spi slave timing (cpha=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure a-9 spi slave timing (cpha=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure a-10 general external bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure b-1 112-pin lqfp mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 124 figure b-2 80-pin qfp mechanical dimensions (case no. 841b) . . . . . . . . . . . . . . . . . . . 125 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 11 list of tables table 0-1 derivative differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 0-2 defects fixed on maskset 1l80r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 0-3 defects fixed on maskset 2l80r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 0-4 document references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 1-1 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 $0000 - $000f mebi map 1 of 3 (hcs12 multiplexed external bus interface) ................29 $0010 - $0014 mmc map 1 of 4 (hcs12 module mapping control) ...............................29 $0015 - $0016 int map 1 of 2 (hcs12 interrupt) ............................................................30 $0017 - $0017 mmc map 2 of 4 (hcs12 module mapping control) ...............................30 $0018 - $0018 reserved ..................................................................................................30 $0019 - $0019 vreg3v3 (voltage regulator) ................................................................30 $001a - $001b miscellaneous peripherals (device user guide, table 1-3 ) ....................30 $001c - $001d mmc map 3 of 4 (hcs12 module mapping control, table 1-4 ) ..............30 $001e - $001e mebi map 2 of 3 (hcs12 multiplexed external bus interface) ................30 $001f - $001f int map 2 of 2 (hcs12 interrupt) ............................................................31 $0020 - $0027 reserved ..................................................................................................31 $0028 - $002f bkp (hcs12 breakpoint) .........................................................................31 $0030 - $0031 mmc map 4 of 4 (hcs12 module mapping control) ...............................31 $0032 - $0033 mebi map 3 of 3 (hcs12 multiplexed external bus interface) ................31 $0034 - $003f crg (clock and reset generator) ..........................................................32 $0040 - $006f tim (timer 16 bit 8 channels) .................................................................32 $0070 - $007f reserved .................................................................................................34 $0080 - $00af atd (analog to digital converter 10 bit 16 channel) ..............................34 $00b0 - $00c7 reserved .................................................................................................36 $00c8 - $00cf sci0 (asynchronous serial interface) ......................................................36 $00d0 - $00d7 sci1 (asynchronous serial interface) ......................................................36 $00d8 - $00df spi0 (serial peripheral interface) ............................................................37 $00e0 - $00e7 iic (inter ic bus) ......................................................................................37 $00e8 - $00ff reserved ..................................................................................................38 $0100 - $010f flash control register (fts128k1) ............................................................38 $0110 - $011b eeprom control register (eets1k) ........................................................39 $011c - $013f reserved ..................................................................................................39 $0140 - $017f can0 (motorola scalable can - mscan) ..............................................39 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 12 table 1-2 detailed mscan foreground receive and transmit buffer layout . . . . . . . . . . .40 $0180 - $01ff reserved ..................................................................................................41 $0200 - $0227 pwm (pulse width modulator 8 bit 8 channel) .......................................42 $0228 - $023f reserved ..................................................................................................43 $0240 - $027f pim (port integration module) ..................................................................43 $0280 - $03ff reserved ..................................................................................................45 table 1-3 assigned part id numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 1-4 memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 2-1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 0 table 2-2 mc9s12b128 power and ground connection summary . . . . . . . . . . . . . . . . . . .60 table 4-1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 table 4-2 clock selection based on pe7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 table 4-3 voltage regulator vregen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 5-1 interrupt vector locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 21-1 suggested external component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 table a-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table a-2 esd and latch-up test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table a-3 esd and latch-up protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 table a-4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 table a-5 thermal package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 table a-6 5v i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 table a-7 3.3v i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 table a-8 supply current characteristics at 25mhz bus frequency. . . . . . . . . . . . . . . . . . .89 table a-9 supply current characteristics at 16mhz bus frequency. . . . . . . . . . . . . . . . . . .90 table a-10 atd operating characteristics in 5v range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 table a-11 atd operating characteristics in 3.3v range . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table a-12 atd electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 table a-13 atd conversion performance in 5v range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table a-14 atd conversion performance in 3.3v range . . . . . . . . . . . . . . . . . . . . . . . . . . .95 table a-15 nvm timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 table a-16 nvm reliability characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 table a-17 vreg_3v3 - operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 table a-18 vreg_3v3 - capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 table a-19 startup characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 table a-20 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 table a-21 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 13 table a-22 mscan wake-up pulse characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 table a-23 measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 table a-24 spi master mode timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 table a-25 spi slave mode timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 table a-26 expanded bus timing characteristics in 5v range . . . . . . . . . . . . . . . . . . . . . .121 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 14 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 15 derivative differences and document references the device user guide provides information about the particular system made up of the mc9s12b128 and mc9s12b64. derivative differences table 0-1 shows the availability of peripheral modules on the various derivatives. for details about using the hcs12 d family as a development platform for the hcs12b family refer also to engineering bulletin eb388. table 0-2 shows the defects fixed on maskset 1l80r. table 0-3 shows the defects fixed on maskset 2l80r. table 0-1 derivative differences generic device mc9s12b128 mc9s12b64 packages 112lqfp, 80qfp 112lqfp, 80qfp mask set l80r l80r temp options m, v, c m, v, c package codes pv, fu pv, fu bus speed options 25mhz, 16mhz 25mhz, 16mhz note an errata exists contact sales of?ce an errata exists contact sales of?ce table 0-2 defects ?xed on maskset 1l80r errata number module affected brief description workaround mucts01096 mscan data byte corrupted in receive buffer yes table 0-3 defects ?xed on maskset 2l80r errata number module affected brief description workaround mucts01096 mscan data byte corrupted in receive buffer yes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 16 figure 0-1 order partnumber example the following items should be considered when using a derivative. ? preliminarymc9s12b64 using mc9s12b128 die the mc9s12b128 is tested only for mc9s12b64 functionality. for the preliminary mc9s12b64 the upper 2k bytes ram of the mc9s12b128 are reserved and should not be used. also the pages $38-$3b of flash are reserved and should not be used. ? pins not available in 80 pin qfp package C port h in order to avoid floating nodes the ports should be either configured as outputs by setting the data direction register (ddrh at base+$0262) to $ff, or enabling the pull resistors by writing a $ff to the pull enable register (perh at base+$0264). C port j[1:0] port j pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). therefore care must be taken not to disable the pull enables on pj[1:0] by clearing the bits perj1 and perj0 at base+$026c. C port k port k pull-up resistors are enabled out of reset, i.e. bit 7 = puke = 1 in the register pucr at base+$000c. therefor care must be taken not to clear this bit. C port m[7:6] pm7:6 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. C port p6 pp6 must be configured as output or its pull resistor must be enabled to avoid a floating input. C port s[7:4] ps7:4 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. mc9s12 b128 c fu 25 package option temperature option device title controller family temperature options c = -40?c to 85?c v = -40?c to 105?c m = -40?c to 125?c package options fu = 80qfp pv = 112lqfp speed speed options 25 = 25mhz bus 16 = 16mhz bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 17 C pad[15:8] (atd channels) out of reset the atd channels to pad[15:8] are disabled preventing current flows in the pins. do not modify the atd registers for these channels! document references the device user guide provides information about the mc9s12b128 device made up of standard hcs12 blocks and the hcs12 processor core. this document is part of the customer documentation. a complete set of device manuals also includes all the individual block user guides of the implemented modules. in a effort to reduce redundancy all module specific information is located only in the respective block user guide. if applicable, special implementation details of the module are given in the block description sections of this document. see table 0-4 for names and versions of the referenced documents throughout the device user guide. table 0-4 document references user guide versi on document order number cpu12 reference manual v02 s12cpu12v2/ad hcs12 module mapping control (mmc) block guide v04 s12mmcv4/d hcs12 multiplexed external bus interface (mebi) block guide v03 s12mebiv3/d hcs12 interrupt (int) block guide v01 s12intv1/d hcs12 background debug (bdm) block guide v04 s12bdmv4/d hcs12 breakpoint (bkp) block guide v01 s12bkpv1/d clock and reset generator (crg) block user guide v04 s12crgv4/d oscillator (osc) block user guide v02 s12oscv2/d input capture/output compare timer (tim_16b8c) block user guide v01 s12tim16b8cv1/d analog to digital converter10 bit 16 channel (atd_10b16c) block user guide v03 s12atd10b16cv3/d inter ic bus (iic) block user guide v02 s12iicv2/d asynchronous serial interface (sci) block user guide v02 s12sciv2/d serial peripheral interface (spi) block user guide v03 s12spiv3/d pulse width modulator 8 bit 8 channel (pwm_8b8c) block user guide v01 s12pwm8b8cv1/d 128k byte flash (fts128k1) block user guide v01 s12fts128k1v1/d 1k byte eeprom (eets1k) block user guide v01 s12eets1kv1/d motorola scalable can (mscan) block user guide v02 s12mscanv2/d voltage regulator (vreg3v3) block user guide v02 s12vreg3v3v2/d port integration module (pim_9b128) block user guide v01 s12pim9b128v1/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 19 section 1 introduction 1.1 overview the mc9s12b128 microcontroller unit (mcu) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (cpu12), 128k bytes of flash eeprom, 4k bytes of ram, 1k bytes of eeprom, two asynchronous serial communications interfaces (sci), serial peripheral interface (spi), an input capture/output compare timer (tim), 16- channel, 10-bit analog-to-digital converter (adc), an 8-channel pulse-width modulator (pwm), one can 2.0 a, b software compatible module (mscan12) and an inter-ic bus. the mc9s12b128 has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. the inclusion of a pll circuit allows power consumption and performance to be adjusted to suit operational requirements. in addition to the i/o ports available in each module, up to 22 i/o ports are available with wake-up capability from stop or wait mode. 1.2 features ? hcs12 core C 16-bit hcs12 cpu i. upward compatible with m68hc11 instruction set ii. interrupt stacking and programmers model identical to m68hc11 iii. instruction queue iv. enhanced indexed addressing C mebi (multiplexed external bus interface) C mmc (module mapping control) C int (interrupt control) C bkp (breakpoints) C bdm (background debug mode) ? crg C low current colpitts or C pierce oscillator, C pll, C cop watchdog, C real time interrupt, C clock monitor ? 8-bit and 4-bit ports with interrupt functionality f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 20 C digital filtering C programmable rising or falling edge trigger ? memory C 128k flash eeprom C 1k byte eeprom C 4k byte ram ? analog-to-digital converter C 16-channels for 112 pin package, 8 channels for 80 pin package options C 10-bit resolution C external conversion trigger capability ? 1m bit per second, can 2.0 a, b software compatible module C five receive and three transmit buffers C flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit C four separate interrupt channels for rx, tx, error and wake-up C low-pass filter wake-up function C loop-back for self test operation ? input capture/output compare timer (tim) C 16-bit counter with 7-bit prescaler C 8 programmable input capture or output compare channels C 16-bit pulse accumulators C simple pwm mode C modulo reset of timer counter C external event counting C gated time accumulation ? 8 pwm channels C programmable period and duty cycle C 8-bit 8-channel or 16-bit 4-channel C separate control for each pulse width and duty cycle C center-aligned or left-aligned outputs C programmable clock select logic with a wide range of frequencies C fast emergency shutdown input C usable as interrupt inputs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 21 ? serial interfaces C two asynchronous serial communications interfaces (sci) C synchronous serial peripheral interface (spi) ? inter-ic bus (iic) C compatible with i2c bus standard C multi-master operation C software programmable for one of 256 different serial clock frequencies ? internal 2.5v regulator C supports an input voltage range from 2.97v to 5.5v C low power mode capability C includes low voltage reset (lvr) circuitry C includes low voltage interrupt (lvi) circuitry ? 112-pin lqfp or 80 qfp package C i/o lines with 5v input and drive capability C 5v a/d converter inputs C operation at 32 mhz equivalent to 16 mhz bus speed; option 50mhz equivalent to 25mhz bus speed C development support C single-wire background debug? mode (bdm) C on-chip hardware breakpoints 1.3 modes of operation user modes ? normal and emulation operating modes C normal single-chip mode C normal expanded wide mode C normal expanded narrow mode C emulation expanded wide mode C emulation expanded narrow mode ? special operating modes C special single-chip mode with active background debug mode C special test mode ( motorola use only ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 22 C special peripheral mode ( motorola use only ) low power modes ? stop mode ? pseudo stop mode ? wait mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 23 1.4 block diagram figure 1-1 shows a block diagram of the mc9s12b128 device. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 24 figure 1-1 mc9s12b128 block diagram 128k byte flash eeprom 4k byte ram input capture reset extal xtal vdd1,2 vss1,2 sci0 1k byte eeprom bkgd r/ w modb xirq noacc/ xclks system integration module (sim) vddr cpu12 periodic interrupt cop watchdog clock monitor single-wire background breakpoints pll vsspll xfc vddpll multiplexed address/data bus vdda vssa vrh vrl atd multiplexed wide bus multiplexed vddx vssx internal logic 2.5v narrow bus ppage vddpll vsspll pll 2.5v irq lstrb eclk moda pa 4 pa 3 pa 2 pa 1 pa 0 pa 7 pa 6 pa 5 test addr12 addr11 addr10 addr9 addr8 addr15 addr14 addr13 data12 data11 data10 data 9 data 8 data15 data14 data13 pb4 pb3 pb2 pb1 pb0 pb7 pb6 pb5 addr4 addr3 addr2 addr1 addr0 addr7 addr6 addr5 data 4 data 3 data 2 data 1 data 0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 data 7 data 6 data 5 pe3 pe4 pe5 pe6 pe7 pe0 pe1 pe2 an2 an6 an0 an7 an1 an3 an4 an5 pad3 pad4 pad5 pad6 pad7 pad0 pad1 pad2 ioc2 ioc6 ioc0 ioc7 ioc1 ioc3 ioc4 ioc5 pt3 pt4 pt5 pt6 pt7 pt0 pt1 pt2 vrh vrl vdda vssa rxd txd miso mosi ps3 ps4 ps5 ps0 ps1 ps2 sci1 rxd txd pwm pwm2 pwm0 pwm1 pwm3 pp3 pp4 pp5 pp6 pp7 pp0 pp1 pp2 pix2 pix0 pix1 pix3 ecs pk3 pk7 pk0 pk1 xaddr17 ecs xaddr14 xaddr15 xaddr16 sck ss ps6 ps7 spi0 pj6 pj7 pm2 pm3 pm4 pm5 pm6 pm7 pin kwh2 kwh6 kwh0 kwh7 kwh1 kwh3 kwh4 kwh5 ph3 ph4 ph5 ph6 ph7 ph0 ph1 ph2 kwj0 kwj1 pj0 pj1 i/o driver 5v vdda vssa a/d converter 5v & ddra ddrb pta ptb ddre pte ad ptk ddrk ptt ddrt ptp ddrp pts ddrs ptm ddrm pth ddrh ptj ddrj pk2 interrupt logic clock and reset generation module voltage regulator vssr debug module vdd1,2 vss1,2 vregen vddr vssr voltage regulator 5v & i/o pix4 pix5 pk4 pk5 xaddr18 xaddr19 voltage regulator reference kwp2 kwp6 kwp0 kwp7 kwp1 kwp3 kwp4 kwp5 kwj6 kwj7 output compare can0 rxcan txcan pm0 pm1 timer an10 an14 an08 an15 an09 an11 an12 an13 pad11 pad12 pad13 pad14 pad15 pad08 pad09 pad10 ad pwm6 pwm4 pwm5 pwm7 iic sda scl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 25 1.5 system memory map table 1-1 and figure 1-2 show the device memory map of the mc9s12b128 after reset. the 1k eeprom is mapped twice in a 2k address space. note that after reset the bottom 1k of the eeprom ($0000 - $03ff) are hidden by the register space, and the 1k $0400 - $07ff is hidden by the ram. table 1-1 device memory map address module size (bytes) $0000 - $000f hcs12 multiplexed external bus interface 16 $0010 - $0014 hcs12 module mapping control 5 $0015 - $0016 hcs12 interrupt 2 $0017 hcs12 module mapping control 1 $0018 reserved 1 $0019 voltage regulator (vreg) 1 $001a - $001b device id register (partid) 2 $001c - $001d hcs12 module mapping control 2 $001e hcs12 multiplexed external bus interface 1 $001f hcs12 interrupt 1 $0020 - $0027 reserved 8 $0028 - $002f hcs12 breakpoint 8 $0030 - $0031 hcs12 module mapping control 2 $0032 - $0033 hcs12 multiplexed external bus interface 2 $0034 - $003f clock and reset generator (pll, rti, cop) 12 $0040 - $006f standard timer module16-bit 8-channels (tim) 48 $0070 - $007f reserved 16 $0080 - $00af analog to digital converter 10-bit 16 channels (atd) 48 $00b0 - $00c7 reserved 24 $00c8 - $00cf serial communications interface 0 (sci0) 8 $00d0 - $00d7 serial communications interface 1 (sci1) 8 $00d8 - $00df serial peripheral interface (spi0) 8 $00e0 - $00e7 inter ic bus (iic) 8 $00e8 - $00ff reserved 24 $0100- $010f flash control register 16 $0110 - $011b eeprom control register 12 $011c - $013f reserved 36 $0140 - $017f motorola scalable can (can0) 64 $0180 - $01ff reserved 128 $0200 - $0227 pwm (pulse width modulator 8 bit 8 channel) 40 $0228 - $023f reserved 24 $0240 - $027f port integration module (pim) 64 $0280 - $03ff reserved 384 $0000 - $07ff eeprom array 1k array mapped twice in the address space 2048 $0000 - $0fff ram array 4096 $0000 - $3fff fixed flash eeprom array 16384 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 26 $4000 - $7fff fixed flash eeprom array incl. 0.5k, 1k, 2k or 4k protected sector at start 16384 $8000 - $bfff flash eeprom page window (eight 16k windows) 16384 $c000 - $ffff fixed flash eeprom array incl. 0.5k, 1k, 2k or 4k protected sector at end and 256 bytes of vector space at $ff80 - $ffff 16384 table 1-1 device memory map address module size (bytes) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 27 figure 1-2 mc9s12b128 memory map out of reset $0400 $0000 $0800 $4000 $8000 $c000 $ff00 vectors $ffff extern expanded vectors normal single chip vectors special single chip registers (mappable to any 2k $0000 $03ff $0000 $07ff 1k bytes eeprom (mappable to any 2k 4k bytes ram (mappable to any 4k $0000 $0fff boundary) $4000 $7fff 16k fixed flash page $3e = 62 (this is dependant on the state of the romhm bit) $8000 $bfff 16k page window 8 x 16k flash eeprom pages $c000 $ffff 16k fixed flash page $3f = 63 $ff00 $ffff bdm (if active) boundary within the first 32k) boundary; 1k mapped two times in the 2k address $1000 space) extern $0000 $3fff 16k fixed flash page $3d = 61 (this is dependant on the state of the romhm bit) $0000-$0fff hidden extern f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 28 figure 1-3 mc9s12b64 using mc9s12b128 die memory map out of reset $0400 $0000 $0800 $4000 $8000 $c000 $ff00 vectors $ffff extern expanded vectors normal single chip vectors special single chip registers (mappable to any 2k $0000 $03ff $0000 $07ff 1k bytes eeprom (mappable to any 2k 4k bytes ram (mappable to any 4k $0000 $0fff boundary) upper 2k of $4000 $7fff 16k fixed flash page $3e = 62 (this is dependant on the state of the romhm bit) $8000 $bfff 16k page window 8 x 16k flash eeprom pages $c000 $ffff 16k fixed flash page $3f = 63 $ff00 $ffff bdm (if active) boundary within the first 32k) boundary; 1k mapped two times in the 2k address $1000 space) extern $0000 $3fff 16k fixed flash page $3d = 61 (this is dependant on the state of the romhm bit) $0000-$0fff hidden extern ram are reserved pages $38-$3b of flash eeprom are reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 29 1.5.1 detailed register map $0000 - $000f mebi map 1 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0000 porta read: bit 7 654321 bit 0 write: $0001 portb read: bit 7 654321 bit 0 write: $0002 ddra read: bit 7 654321 bit 0 write: $0003 ddrb read: bit 7 654321 bit 0 write: $0004 reserved read: 00000000 write: $0005 reserved read: 00000000 write: $0006 reserved read: 00000000 write: $0007 reserved read: 00000000 write: $0008 porte read: bit 7 65432 bit 1 bit 0 write: $0009 ddre read: bit 7 6543 bit 2 00 write: $000a pear read: noacce 0 pipoe neclk lstre rdwe 00 write: $000b mode read: modc modb moda 0 ivis 0 emk eme write: $000c pucr read: pupke 00 pupee 00 pupbe pupae write: $000d rdriv read: rdpk 00 rdpe 00 rdpb rdpa write: $000e ebictl read: 0000000 estr write: $000f reserved read: 00000000 write: $0010 - $0014 mmc map 1 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0010 initrm read: ram15 ram14 ram13 ram12 ram11 00 ramhal write: $0011 initrg read: 0 reg14 reg13 reg12 reg11 000 write: $0012 initee read: ee15 ee14 ee13 ee12 ee11 00 eeon write: $0013 misc read: 0000 exstr1 exstr0 romhm romon write: $0014 reserved read: 00000000 write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 30 $0015 - $0016 int map 1 of 2 (hcs12 interrupt) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0015 itcr read: 0 0 0 wrint adr3 adr2 adr1 adr0 write: $0016 itest read: inte intc inta int8 int6 int4 int2 int0 write: $0017 - $0017 mmc map 2 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0017 reserved read: 00000000 write: $0018 - $0018 reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0018 reserved read: 00000000 write: $0019 - $0019 vreg3v3 (voltage regulator) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0019 vregctrl read: 00000lvds lvie lvif write: $001a - $001b miscellaneous peripherals (device user guide, table 1-3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001a partidh read: id15 id14 id13 id12 id11 id10 id9 id8 write: $001b partidl read: id7 id6 id5 id4 id3 id2 id1 id0 write: $001c - $001d mmc map 3 of 4 (hcs12 module mapping control, table 1-4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001c memsiz0 read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0 write: $001d memsiz1 read: rom_sw1 rom_sw0 0000 pag_sw1 pag_sw0 write: $001e - $001e mebi map 2 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001e intcr read: irqe irqen 000000 write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 31 $001f - $001f int map 2 of 2 (hcs12 interrupt) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001f hprio read: psel7 psel6 psel5 psel4 psel3 psel2 psel1 0 write: $0020 - $0027 reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0020 - $0027 reserved read: 00000000 write: $0028 - $002f bkp (hcs12 breakpoint) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0028 bkpct0 read: bken bkfull bkbdm bktag 0000 write: $0029 bkpct1 read: bk0mbh bk0mbl bk1mbh bk1mbl bk0rwe bk0rw bk1rwe bk1rw write: $002a bkp0x read: 0 0 bk0v5 bk0v4 bk0v3 bk0v2 bk0v1 bk0v0 write: $002b bkp0h read: bit 15 14 13 12 11 10 9 bit 8 write: $002c bkp0l read: bit 7 654321 bit 0 write: $002d bkp1x read: 0 0 bk1v5 bk1v4 bk1v3 bk1v2 bk1v1 bk1v0 write: $002e bkp1h read: bit 15 14 13 12 11 10 9 bit 8 write: $002f bkp1l read: bit 7 654321 bit 0 write: $0030 - $0031 mmc map 4 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0030 ppage read: 0 0 pix5 pix4 pix3 pix2 pix1 pix0 write: $0031 reserved read: 00000000 write: $0032 - $0033 mebi map 3 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0032 portk read: bit 7 654321 bit 0 write: $0033 ddrk read: bit 7 654321 bit 0 write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 32 $0034 - $003f crg (clock and reset generator) $0040 - $006f tim (timer 16 bit 8 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0034 synr read: 0 0 syn5 syn4 syn3 syn2 syn1 syn0 write: $0035 refdv read: 0000 refdv3 refdv2 refdv1 refdv0 write: $0036 ctflg test only read: 00000000 write: $0037 crgflg read: rtif porf lvrf lockif lock track scmif scm write: $0038 crgint read: rtie 00 lockie 00 scmie 0 write: $0039 clksel read: pllsel pstp syswai roawai pllwai cwai rtiwai copwai write: $003a pllctl read: cme pllon auto acq 0 pre pce scme write: $003b rtictl read: 0 rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 write: $003c copctl read: wcop rsbck 000 cr2 cr1 cr0 write: $003d forbyp test only read: 00000000 write: $003e ctctl test only read: 00000000 write: $003f armcop read: 00000000 write: bit 7 654321 bit 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0040 tios read: ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 write: $0041 cforc read: 00000000 write: foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 $0042 oc7m read: oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 write: $0043 oc7d read: oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 write: $0044 tcnt (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0045 tcnt (lo) read: bit 7 654321 bit 0 write: $0046 tscr1 read: ten tswai tsfrz tffca 0000 write: $0047 ttov read: tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 write: $0048 tctl1 read: om7 ol7 om6 ol6 om5 ol5 om4 ol4 write: $0049 tctl2 read: om3 ol3 om2 ol2 om1 ol1 om0 ol0 write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 33 $004a tctl3 read: edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a write: $004b tctl4 read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a write: $004c tie read: c7i c6i c5i c4i c3i c2i c1i c0i write: $004d tscr2 read: toi 000 tcre pr2 pr1 pr0 write: $004e tflg1 read: c7f c6f c5f c4f c3f c2f c1f c0f write: $004f tflg2 read: tof 0000000 write: $0050 tc0 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0051 tc0 (lo) read: bit 7 654321 bit 0 write: $0052 tc1 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0053 tc1 (lo) read: bit 7 654321 bit 0 write: $0054 tc2 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0055 tc2 (lo) read: bit 7 654321 bit 0 write: $0056 tc3 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0057 tc3 (lo) read: bit 7 654321 bit 0 write: $0058 tc4 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0059 tc4 (lo) read: bit 7 654321 bit 0 write: $005a tc5 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005b tc5 (lo) read: bit 7 654321 bit 0 write: $005c tc6 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005d tc6 (lo) read: bit 7 654321 bit 0 write: $005e tc7 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005f tc7 (lo) read: bit 7 654321 bit 0 write: $0060 pactl read: 0 paen pamod pedge clk1 clk0 paovi pai write: $0061 paflg read: 000000 paovf paif write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 34 $0070 - $007f reserved $0062 pacnt (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0063 pacnt (lo) read: bit 7 654321 bit 0 write: $0064- $006f reserved read: 00000000 write: $0070 - $007f reserved read: 00000000 write: $0080 - $00af atd (analog to digital converter 10 bit 16 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0080 atdctl0 read: 0000 wrap3 wrap2 wrap1 wrap0 write: $0081 atdctl1 read: etrig- sel 000 etrigc h3 etrigc h2 etrigc h1 etrigc h0 write: $0082 atdctl2 read: adpu affc awai etrigle etrigp etrig ascie ascif write: $0083 atdctl3 read: 0 s8c s4c s2c s1c fifo frz1 frz0 write: $0084 atdctl4 read: sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 write: $0085 atdctl5 read: djm dsgn scan mult cd cc cb ca write: $0086 atdstat0 read: scf 0 etorf fifor cc3 cc2 cc1 cc0 write: $0087 reserved read: 00000000 write: $0088 atdtest0 read: 00000000 write: $0089 atdtest1 read: 0000000 sc write: $008a atdstat2 read: ccf15 ccf14 ccf13 ccf12 ccf11 ccf10 ccf9 ccf8 write: $008b atdstat1 read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: $008c atddien0 read: ien15 ien14 ien13 ien12 ien11 ien10 ien9 ien8 write: $008d atddien1 read: ien7 ien6 ien5 ien4 ien3 ien2 ien1 ien0 write: $008e portad0 read: ptad15 ptad14 ptad13 ptad12 ptad11 ptad10 ptad9 ptad8 write: $008f portad1 read: ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 write: $0090 atddr0h read: bit15 14 13 12 11 10 9 bit8 write: $0091 atddr0l read: bit7 bit6 000000 write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 35 $0092 atddr1h read: bit15 14 13 12 11 10 9 bit8 write: $0093 atddr1l read: bit7 bit6 000000 write: $0094 atddr2h read: bit15 14 13 12 11 10 9 bit8 write: $0095 atddr2l read: bit7 bit6 000000 write: $0096 atddr3h read: bit15 14 13 12 11 10 9 bit8 write: $0097 atddr3l read: bit7 bit6 000000 write: $0098 atddr4h read: bit15 14 13 12 11 10 9 bit8 write: $0099 atddr4l read: bit7 bit6 000000 write: $009a atddr5h read: bit15 14 13 12 11 10 9 bit8 write: $009b atddr5l read: bit7 bit6 000000 write: $009c atddr6h read: bit15 14 13 12 11 10 9 bit8 write: $009d atddr6l read: bit7 bit6 000000 write: $009e atddr7h read: bit15 14 13 12 11 10 9 bit8 write: $009f atddr7l read: bit7 bit6 000000 write: $00a0 atddr8h read: bit15 14 13 12 11 10 9 bit8 write: $00a1 atddr8l read: bit7 bit6 000000 write: $00a2 atddr9h read: bit15 14 13 12 11 10 9 bit8 write: $00a3 atddr9l read: bit7 bit6 000000 write: $00a4 atddr10h read: bit15 14 13 12 11 10 9 bit8 write: $00a5 atddr10l read: bit7 bit6 000000 write: $00a6 atddr11h read: bit15 14 13 12 11 10 9 bit8 write: $00a7 atddr11l read: bit7 bit6 000000 write: $00a8 atddr12h read: bit15 14 13 12 11 10 9 bit8 write: $00a9 atddr12l read: bit7 bit6 000000 write: $00aa atddr13h read: bit15 14 13 12 11 10 9 bit8 write: $0080 - $00af atd (analog to digital converter 10 bit 16 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 36 $00b0 - $00c7 reserved $00ab atddr13l read: bit7 bit6 000000 write: $00ac atddr14h read: bit15 14 13 12 11 10 9 bit8 write: $00ad atddr14l read: bit7 bit6 000000 write: $00ae atddr15h read: bit15 14 13 12 11 10 9 bit8 write: $00af atddr15l read: bit7 bit6 000000 write: $00b0 - $00c7 reserved read: 00000000 write: $00c8 - $00cf sci0 (asynchronous serial interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00c8 sci0bdh read: 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $00c9 sci0bdl read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $00ca sci0cr1 read: loops sciswai rsrc m wake ilt pe pt write: $00cb sci0cr2 read: tie tcie rie ilie te re rwu sbk write: $00cc sci0sr1 read: tdre tc rdrf idle or nf fe pf write: $00cd sci0sr2 read: 00000 brk13 txdir raf write: $00ce sci0drh read: r8 t8 000000 write: $00cf sci0drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $00d0 - $00d7 sci1 (asynchronous serial interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00d0 sci1bdh read: 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $00d1 sci1bdl read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $00d2 sci1cr1 read: loops sciswai rsrc m wake ilt pe pt write: $00d3 sci1cr2 read: tie tcie rie ilie te re rwu sbk write: $0080 - $00af atd (analog to digital converter 10 bit 16 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 37 $00d4 sci1sr1 read: tdre tc rdrf idle or nf fe pf write: $00d5 sci1sr2 read: 00000 brk13 txdir raf write: $00d6 sci1drh read: r8 t8 000000 write: $00d7 sci1drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $00d8 - $00df spi0 (serial peripheral interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00d8 spi0cr1 read: spie spe sptie mstr cpol cpha ssoe lsbfe write: $00d9 spi0cr2 read: 0 0 0 modfen bidiroe 0 spiswai spc0 write: $00da spi0br read: 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 write: $00db spi0sr read: spif 0 sptef modf 0000 write: $00dc reserved read: 00000000 write: $00dd spi0dr read: bit7 654321 bit0 write: $00de reserved read: 00000000 write: $00df reserved read: 00000000 write: $00e0 - $00e7 iic (inter ic bus) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00e0 ibad read: adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 write: $00e1 ibfd read: ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 write: $00e2 ibcr read: iben ibie ms/ sl tx/ rx txak 00 ibswai write: rsta $00e3 ibsr read: tcf iaas ibb ibal 0srw ibif rxak write: $00e4 ibdr read: d7 d6 d5 d4 d3 d2 d1 d0 write: $00d0 - $00d7 sci1 (asynchronous serial interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 38 $00e5 reserved read: 0 0 0 0 0 0 0 0 write: $00e6 reserved read: 00000000 write: $00e7 reserved read: 00000000 write: $00e8 - $00ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00e8 - $00ff reserved read: 00000000 write: $0100 - $010f flash control register (fts128k1) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0100 fclkdiv read: fdivld prdiv8 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 write: $0101 fsec read: keyen1 keyen0 nv5 nv4 nv3 nv2 sec1 sec0 write: $0102 reserved read: 00000000 write: $0103 fcnfg read: cbeie ccie keyacc 00000 write: $0104 fprot read: fpopen nv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 write: $0105 fstat read: cbeif ccif pviol accerr 0 blank 00 write: $0106 fcmd read: 0 cmdb6 cmdb5 00 cmdb2 0 cmdb0 write: $0107 reserved read: 00000000 write: $0108 faddrhi read: bit 15 bit 14 13 12 11 10 9 bit 8 write: $0109 faddrlo read: bit 7 654321 bit 0 write: $010a fdatahi read: bit 15 14 13 12 11 10 9 bit 8 write: $010b fdatalo read: bit 7 654321 bit 0 write: $010c - $010f reserved read: 00000000 write: $00e0 - $00e7 iic (inter ic bus) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 39 $0110 - $011b eeprom control register (eets1k) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0110 eclkdiv read: edivld prdiv8 ediv5 ediv4 ediv3 ediv2 ediv1 ediv0 write: $0111 reserved read: 00000000 write: $0112 reserved read: 00000000 write: $0113 ecnfg read: cbeie ccie 000000 write: $0114 eprot read: epopen nv6 nv5 nv4 epdis ep2 ep1 ep0 write: $0115 estat read: cbeif ccif pviol accerr 0 blank 0 0 write: $0116 ecmd read: 0 cmdb6 cmdb5 00 cmdb2 0 cmdb0 write: $0117 reserved read: 00000000 write: $0118 eaddrhi read: 0000000 bit8 write: $0119 eaddrlo read: bit7 654321 bit0 write: $011a edatahi read: bit15 14 13 12 11 10 9 bit8 write: $011b edatalo read: bit7 654321 bit0 write: $011c - $013f reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $011c - $013f reserved read: 00000000 write: $0140 - $017f can0 (motorola scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0140 can0ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0141 can0ctl1 read: cane clksrc loopb listen 0 wupm slpak initak write: $0142 can0btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0143 can0btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0144 can0rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $0145 can0rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0146 can0tflg read: 00000 txe2 txe1 txe0 write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 40 $0147 can0tier read: 00000 txeie2 txeie1 txeie0 write: $0148 can0tarq read: 00000 abtrq2 abtrq1 abtrq0 write: $0149 can0taak read: 00000abtak2abtak1abtak0 write: $014a can0tbsel read: 00000 tx2 tx1 tx0 write: $014b can0idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $014c reserved read: 00000000 write: $014d reserved read: 00000000 write: $014e can0rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $014f can0txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0150 - $0153 can0idar0 - can0idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0154 - $0157 can0idmr0 - can0idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0158 - $015b can0idar4 - can0idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $015c - $015f can0idmr4 - can0idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0160 - $016f can0rxfg read: foreground receive buffer see table 1-2 write: $0170 - $017f can0txfg read: foreground transmit buffer see table 1-2 write: table 1-2 detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0160 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 standard id read: id10 id9 id8 id7 id6 id5 id4 id3 can0ridr0 write: $0161 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 standard id read: id2 id1 id0 rtr ide=0 can0ridr1 write: $0162 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 standard id read: can0ridr2 write: $0163 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr standard id read: can0ridr3 write: $0164- $016b can0rdsr0 - can0rdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $0140 - $017f can0 (motorola scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 41 $016c can0rdlr read: dlc3 dlc2 dlc1 dlc0 write: $016d reserved read: write: $016e can0rtsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $016f can0rtsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $0170 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 can0tidr0 write: standard id read: id10 id9 id8 id7 id6 id5 id4 id3 write: $0171 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 can0tidr1 write: standard id read: id2 id1 id0 rtr ide=0 write: $0172 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 can0tidr2 write: standard id read: write: $0173 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr can0tidr3 write: standard id read: write: $0174- $017b can0tdsr0 - can0tdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $017c can0tdlr read: dlc3 dlc2 dlc1 dlc0 write: $017d can0ttbpr read: prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 write: $017e can0ttsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $017f can0ttsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $0180 - $01ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0180 - $01ff reserved read: 00000000 write: table 1-2 detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 42 $0200 - $0227 pwm (pulse width modulator 8 bit 8 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0200 pwme read: pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 write: $0201 pwmpol read: ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 write: $0202 pwmclk read: pclk7 pclk6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 write: $0203 pwmprclk read: 0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 write: $0204 pwmcae read: cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 write: $0205 pwmctl read: con67 con45 con23 con01 pswai pfrz 00 write: $0206 pwmtst test only read: 00000000 write: $0207 pwmprsc test only read: 00000000 write: $0208 pwmscla read: bit 7 6 5 4 3 2 1 bit 0 write: $0209 pwmsclb read: bit 7 6 5 4 3 2 1 bit 0 write: $020a pwmscnta test only read: 00000000 write: $020b pwmscntb test only read: 00000000 write: $020c pwmcnt0 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $020d pwmcnt1 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $020e pwmcnt2 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $020f pwmcnt3 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $0210 pwmcnt4 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $0211 pwmcnt5 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $0212 pwmcnt6 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $0213 pwmcnt7 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $0214 pwmper0 read: bit 7 6 5 4 3 2 1 bit 0 write: $0215 pwmper1 read: bit 7 6 5 4 3 2 1 bit 0 write: $0216 pwmper2 read: bit 7 6 5 4 3 2 1 bit 0 write: $0217 pwmper3 read: bit 7 6 5 4 3 2 1 bit 0 write: $0218 pwmper4 read: bit 7 6 5 4 3 2 1 bit 0 write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 43 $0219 pwmper5 read: bit 7 6 5 4 3 2 1 bit 0 write: $021a pwmper6 read: bit 7 6 5 4 3 2 1 bit 0 write: $021b pwmper7 read: bit 7 6 5 4 3 2 1 bit 0 write: $021c pwmdty0 read: bit 7 6 5 4 3 2 1 bit 0 write: $021d pwmdty1 read: bit 7 6 5 4 3 2 1 bit 0 write: $021e pwmdty2 read: bit 7 6 5 4 3 2 1 bit 0 write: $021f pwmdty3 read: bit 7 6 5 4 3 2 1 bit 0 write: $0220 pwmdty4 read: bit 7 6 5 4 3 2 1 bit 0 write: $0221 pwmdty5 read: bit 7 6 5 4 3 2 1 bit 0 write: $0222 pwmdty6 read: bit 7 6 5 4 3 2 1 bit 0 write: $0223 pwmdty7 read: bit 7 6 5 4 3 2 1 bit 0 write: $0224 pwmsdn read: pwmif pwmie 0 pwmlvl 0 pwm7in pwm7inl pwm7ena write: pwmrstrt $0225- $0227 reserved read: 00000000 write: $0228 - $023f reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0228 - $023f reserved read: 00000000 write: $0240 - $027f pim (port integration module) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0240 ptt read: ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 write: $0241 ptit read: ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 write: $0242 ddrt read: ddrt7 ddrt7 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 write: $0243 rdrt read: rdrt7 rdrt6 rdrt5 rdrt4 rdrt3 rdrt2 rdrt1 rdrt0 write: $0244 pert read: pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 write: $0245 ppst read: ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 write: $0200 - $0227 pwm (pulse width modulator 8 bit 8 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 44 $0246 reserved read: 00000000 write: $0247 reserved read: 00000000 write: $0248 pts read: pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 write: $0249 ptis read: ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 write: $024a ddrs read: ddrs7 ddrs7 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 write: $024b rdrs read: rdrs7 rdrs6 rdrs5 rdrs4 rdrs3 rdrs2 rdrs1 rdrs0 write: $024c pers read: pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 write: $024d ppss read: ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 write: $024e woms read: woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 write: $024f reserved read: 00000000 write: $0250 ptm read: ptm7 ptm6 ptm5 ptm4 ptm3 ptm2 ptm1 ptm0 write: $0251 ptim read: ptim7 ptim6 ptim5 ptim4 ptim3 ptim2 ptim1 ptim0 write: $0252 ddrm read: ddrm7 ddrm7 ddrm5 ddrm4 ddrm3 ddrm2 ddrm1 ddrm0 write: $0253 rdrm read: rdrm7 rdrm6 rdrm5 rdrm4 rdrm3 rdrm2 rdrm1 rdrm0 write: $0254 perm read: perm7 perm6 perm5 perm4 perm3 perm2 perm1 perm0 write: $0255 ppsm read: ppsm7 ppsm6 ppsm5 ppsm4 ppsm3 ppsm2 ppsm1 ppsm0 write: $0256 womm read: womm7 womm6 womm5 womm4 womm3 womm2 womm1 womm0 write: $0257 modrr read: 0 0 0 modrr4 0000 write: $0258 ptp read: ptp7 ptp6 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 write: $0259 ptip read: ptip7 ptip6 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 write: $025a ddrp read: ddrp7 ddrp7 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 write: $025b rdrp read: rdrp7 rdrp6 rdrp5 rdrp4 rdrp3 rdrp2 rdrp1 rdrp0 write: $025c perp read: perp7 perp6 perp5 perp4 perp3 perp2 perp1 perp0 write: $025d ppsp read: ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppss0 write: $025e piep read: piep7 piep6 piep5 piep4 piep3 piep2 piep1 piep0 write: $0240 - $027f pim (port integration module) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 45 $025f pifp read: pifp7 pifp6 pifp5 pifp4 pifp3 pifp2 pifp1 pifp0 write: $0260 pth read: pth7 pth6 pth5 pth4 pth3 pth2 pth1 pth0 write: $0261 ptih read: ptih7 ptih6 ptih5 ptih4 ptih3 ptih2 ptih1 ptih0 write: $0262 ddrh read: ddrh7 ddrh7 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 write: $0263 rdrh read: rdrh7 rdrh6 rdrh5 rdrh4 rdrh3 rdrh2 rdrh1 rdrh0 write: $0264 perh read: perh7 perh6 perh5 perh4 perh3 perh2 perh1 perh0 write: $0265 ppsh read: ppsh7 ppsh6 ppsh5 ppsh4 ppsh3 ppsh2 ppsh1 ppsh0 write: $0266 pieh read: pieh7 pieh6 pieh5 pieh4 pieh3 pieh2 pieh1 pieh0 write: $0267 pifh read: pifh7 pifh6 pifh5 pifh4 pifh3 pifh2 pifh1 pifh0 write: $0268 ptj read: ptj7 ptj6 0000 ptj1 ptj0 write: $0269 ptij read: ptij7 ptij6 0000 ptij1 ptij0 write: $026a ddrj read: ddrj7 ddrj7 0000 ddrj1 ddrj0 write: $026b rdrj read: rdrj7 rdrj6 0000 rdrj1 rdrj0 write: $026c perj read: perj7 perj6 0000 perj1 perj0 write: $026d ppsj read: ppsj7 ppsj6 0000 ppsj1 ppsj0 write: $026e piej read: piej7 piej6 0000 piej1 piej0 write: $026f pifj read: pifj7 pifj6 0000 pifj1 pifj0 write: $0270 - $027f reserved read: 00000000 write: $0280 - $03ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0280 - $03ff reserved read: 00000000 write: $0240 - $027f pim (port integration module) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 46 1.6 part id assignments the part id is located in two 8-bit registers partidh and partidl (addresses $001a and $001b after reset). the read-only value is a unique part id for each revision of the chip. table 1-3 shows the assigned part id number. the device memory sizes are located in two 8-bit registers memsiz0 and memsiz1 (addresses $001c and $001d after reset). table 1-4 shows the read-only values of these registers. refer to hcs12 module mapping control (mmc) block guide for further details. table 1-3 assigned part id numbers device mask set number part id 1 notes : 1. the coding is as follows: bit 15-12: major family identifier bit 11-8: minor family identifier bit 7-4: major mask set revision number including fab transfers bit 3-0: minor - non full - mask set revision mc9s12b128 0l80r $2100 mc9s12b128 1l80r $2101 mc9s12b128 2l80r $2102 table 1-4 memory size registers register name value memsiz0 $11 memsiz1 $c0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 47 section 2 signal description this section describes signals that connect off-chip. it includes a pinout diagram, a table of signal properties and detailed discussion of signals. it is built from the signal description sections of the block user guides of the individual ip blocks on the device. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 48 2.1 system pinout the mc9s12b128 is available in a 112-pin low profile quad flat pack (lqfp) and in a 80-pin quad flat pack (qfp). most pins perform two or more functions, as described in the signal descriptions. figure 2-1 and figure 2-2 show the pin assignments. figure 2-1 pin assignments in 112-pin lqfp for mc9s12b128 vrh vdda pad15/an15 pad07/an07 pad14/an14 pad06/an06 pad13/an13 pad05/an05 pad12/an12 pad04/an04 pad11/an11 pad03/an03 pad10/an10 pad02/an02 pad09/an09 pad01/an01 pad08/an08 pad00/an00 vss2 vdd2 pa7/addr15/data15 pa6/addr14/data14 pa5/addr13/data13 pa4/addr12/data12 pa3/addr11/data11 pa2/addr10/data10 pa1/addr9/data9 pa0/addr8/data8 pp4/kwp4/pwm4 pp5/kwp5/pwm5 pp6/kwp6/pwm6 pp7/kwp7/pwm7 pk7/ ecs vddx vssx pm0/rxcan0 pm1/txcan0 pm2/miso pm3/ ss pm4/mosi pm5/sck pj6/kwj6/sda pj7/kwj7/scl vregen ps7/ ss0 ps6/sck0 ps5/mosi0 ps4/miso0 ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 pm6 pm7 vssa vrl pwm3/kwp3/pp3 pwm2/kwp2/pp2 pwm1/kwp1/pp1 pwm0/kwp0/pp0 xaddr17/pk3 xaddr16/pk2 xaddr15/pk1 xaddr14/pk0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vdd1 vss1 ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 xaddr19/pk5 xaddr18/pk4 kwj1/pj1 kwj0/pj0 modc/ t a ghi/bkgd addr0/data0/pb0 addr1/data1/pb1 addr2/data2/pb2 addr3/data3/pb3 addr4/data4/pb4 addr5/data5/pb5 addr6/data6/pb6 addr7/data7/pb7 kwh7/ph7 kwh6/ph6 kwh5/ph5 kwh4/ph4 xclks/noacc/pe7 modb/ipipe1/pe6 moda/ipipe0/pe5 eclk/pe4 vssr vddr reset v ddpll xfc vsspll extal xtal test kwh3/ph3 kwh2/ph2 kwh1/ph1 kwh0/ph0 lstrb/ t a glo/pe3 r/ w/pe2 irq/pe1 xirq/pe0 signals shown in bold are not available on the 80 pin package mc9s12b128 112lqfp 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 49 figure 2-2 pin assignments in 80-pin qfp for mc9s12b128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 mc9s12b128 80 qfp vrh vdda pad07/an07 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 vss2 vdd2 pa7/addr15/data15 pa6/addr14/data14 pa5/addr13/data13 pa4/addr12/data12 pa3/addr11/data11 pa2/addr10/data10 pa1/addr9/data9 pa0/addr8/data8 pp4/kwp4/pwm4 pp5/kwp5/pwm5 pp7/kwp7/pwm7 vddx vssx pm0/rxcan0 pm1/txcan0 pm2/miso pm3/ ss pm4/mosi pm5/sck pj6/kwj6/sda pj7/kwj7/scl vregen ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 vssa vrl pwm3/kwp3/pp3 pwm2/kwp2/pp2 pwm1/kwp1/pp1 pwm0/kwp0/pp0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vdd1 vss1 ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 modc/ t a ghi/bkgd addr0/data0/pb0 addr1/data1/pb1 addr2/data2/pb2 addr3/data3/pb3 addr4/data4/pb4 addr5/data5/pb5 addr6/data6/pb6 addr7/data7/pb7 xclks/noacc/pe7 modb/ipipe1/pe6 moda/ipipe0/pe5 eclk/pe4 v ssr v ddr reset v ddpll xfc v sspll extal xtal test lstrb/ t a glo/pe3 r/ w/pe2 irq/pe1 xirq/pe0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 50 2.1.1 signal properties summary table 2-1 summarizes the pin functionality. signals shown in bold are not available in the 80 pin package. table 2-1 signal properties pin name function1 pin name function2 pin name function 3 pin name function 4 powered by internal pull resistor description ctrl reset state extal vddpll none none oscillator pins xtal reset vddr external reset test n.a. test input vregen vddx voltage regulator enable input xfc vddpll pll loop filter bkgd t a ghi modc vddr always up up background debug, tag high, mode input pad[15:8] an[15:8] vdda none none port ad inputs, analog inputs an[15:8] of atd pad[07:00] an[07:00] port ad inputs, analog inputs an[7:0] of atd pa[7:0] addr[15:8]/ data[15:8] vddr pucr/ pupae disabled port a i/o, multiplexed address/data pb[7:0] addr[7:0]/ data[7:0] pucr/ pupbe port b i/o, multiplexed address/data pe7 noacc xclks pucr/ pupee up port e i/o, access, clock select pe6 ipipe1 modb while reset pin is low: down port e i/o, pipe status, mode input pe5 ipipe0 moda port e i/o, pipe status, mode input pe4 eclk pucr/ pupee mode depende nt 1 port e i/o, bus clock output pe3 lstrb t a glo port e i/o, byte strobe, tag low pe2 r/ w port e i/o, r/ w in expanded modes pe1 irq up port e input, maskable interrupt pe0 xirq port e input, non maskable interrupt ph7 kwh7 perh/ ppsh disabled port h i/o, interrupt ph6 kwh6 port h i/o, interrupt ph5 kwh5 port h i/o, interrupt ph4 kwh4 port h i/o, interrupt ph3 kwh3 port h i/o, interrupt ph2 kwh2 port h i/o, interrupt ph1 kwh1 port h i/o, interrupt ph0 kwh0 port h i/o, interrupt pj7 kwj7 scl vddx perj/ ppsj up port j i/o, interrupt, scl of iic, pj6 kwj6 sda port j i/o, interrupt, sda of iic, pj[1:0] kwj[1:0] port j i/o, interrupts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 51 2.2 detailed signal descriptions 2.2.1 extal, xtal oscillator pins extal and xtal are the crystal driver and external clock pins. on reset all the device clocks are derived from the extal input frequency. xtal is the crystal output. pk7 ecs romctl vddx pucr/ pupke up port k i/o, emulation chip select, rom on enable pk[5:0] xaddr[19:14] port k i/o, extended addresses pm7 perm/ ppsm disabled port m i/o pm6 port m i/o pm5 sck port m i/o, sck of spi0 pm4 mosi port m i/o, mosi of spi0 pm3 ss0 port m i/o, ss of spi0 pm2 miso0 port m i/o, miso of spi0 pm1 txcan0 port m i/o, tx of can0 pm0 rxcan0 port m i/o, rx of can0 pp7 kwp7 pwm7 perp/ ppsp port p i/o, interrupt, channel 7 of pwm pp6 kwp6 pwm6 port p i/o, interrupt, pwm channel 6 pp5 kwp5 pwm5 port p i/o, interrupt, pwm channel 5 pp4 kwp4 pwm4 port p i/o, interrupt, pwm channel 4 pp3 kwp3 pwm3 port p i/o, interrupt, pwm channel 3 pp2 kwp2 pwm2 port p i/o, interrupt, pwm channel 2 pp1 kwp1 pwm1 port p i/o, interrupt, pwm channel 1 pp0 kwp0 pwm0 port p i/o, interrupt, pwm channel 0 ps7 ss0 pers/ ppss up port s i/o, ss of spi0 ps6 sck0 port s i/o, sck of spi0 ps5 mosi0 port s i/o, mosi of spi0 ps4 miso0 port s i/o, miso of spi0 ps3 txd1 port s i/o, txd of sci1 ps2 rxd1 port s i/o, rxd of sci1 ps1 txd0 port s i/o, txd of sci0 ps0 rxd0 port s i/o, rxd of sci0 pt[7:0] ioc[7:0] pert/ ppst disabled port t i/o, timer channels notes : 1. refer to pear register description in hcs12 multiplexed external bus interface (mebi) block guide. pin name function1 pin name function2 pin name function 3 pin name function 4 powered by internal pull resistor description ctrl reset state f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 52 2.2.2 reset external reset pin an active low bidirectional control signal, it acts as an input to initialize the mcu to a known start-up state, and an output when an internal mcu function causes a reset. 2.2.3 test test pin this input only pin is reserved for test. note: the test pin must be tied to vss in all applications. 2.2.4 vregen voltage regulator enable pin this input only pin enables or disables the on-chip voltage regulator. 2.2.5 xfc pll loop filter pin pll loop filter. please ask your motorola representative for the interactive application note to compute pll loop filter elements. any current leakage on this pin must be avoided. figure 2-3 pll loop filter connections 2.2.6 bkgd / taghi / modc background debug, tag high, and mode pin the bkgd/ taghi/modc pin is used as a pseudo-open-drain pin for the background debug communication. in mcu expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of e-clock tags the high half of the instruction word being read into the instruction queue. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modc bit at the rising edge of reset. this pin has a permanently enabled pull-up device. 2.2.7 pad[15:0] / an[15:0] port ad input pins atd pad15 - pad0 are general purpose input pins and analog inputs an[15:0] of the analog to digital converter atd. mcu xfc r 0 c s c p vddpll vddpll f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 53 2.2.8 pa[7:0] / addr[15:8] / data[15:8] port a i/o pins pa7-pa0 are general purpose input or output pins. in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. 2.2.9 pb[7:0] / addr[7:0] / data[7:0] port b i/o pins pb7-pb0 are general purpose input or output pins. in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. 2.2.10 pe7 / noacc / xclks port e i/o pin 7 pe7 is a general purpose input or output pin. during mcu expanded modes of operation, the noacc signal, when enabled, is used to indicate that the current bus cycle is an unused or free cycle. this signal will assert when the cpu is not using the bus. the xclks is an input signal which controls whether a crystal in combination with the internal colpitts (low power) oscillator is used or whether pierce oscillator/external clock circuitry is used. the state of this pin is latched at the rising edge of reset. if the input is a logic low the extal pin is configured for an external clock drive or a pierce oscillator. if input is a logic high a colpitts oscillator circuit is configured on extal and xtal. since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is a colpitts oscillator circuit on extal and xtal. figure 2-4 colpitts oscillator connections (pe7=1) mcu c 2 extal xtal crystal or vsspll ceramic resonator c 1 c dc * * due to the nature of a translated ground colpitts oscillator a dc voltage bias is applied to the crystal bias conditions and recommended capacitor value c dc . please contact the crystal manufacturer for crystal dc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 54 figure 2-5 pierce oscillator connections (pe7=0) figure 2-6 external clock connections (pe7=0) 2.2.11 pe6 / modb / ipipe1 port e i/o pin 6 pe6 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modb bit at the rising edge of reset. this pin is shared with the instruction queue tracking signal ipipe1. this pin is an input with a pull-down device which is only active when reset is low. 2.2.12 pe5 / moda / ipipe0 port e i/o pin 5 pe5 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the moda bit at the rising edge of reset. this pin is shared with the instruction queue tracking signal ipipe0. this pin is an input with a pull-down device which is only active when reset is low. 2.2.13 pe4 / eclk port e i/o pin 4 pe4 is a general purpose input or output pin. it can be configured to drive the internal bus clock eclk. eclk can be used as a timing reference. mcu extal xtal r s * r b vsspll crystal or ceramic resonator c 4 c 3 * rs can be zero (shorted) when used with higher frequency crystals. refer to manufacturers data. mcu extal xtal cmos-compatible external oscillato r not connected (v ddpll -level) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 55 2.2.14 pe3 / lstrb / taglo port e i/o pin 3 pe3 is a general purpose input or output pin. in mcu expanded modes of operation, lstrb can be used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, taglo is used to tag the low half of the instruction word being read into the instruction queue. 2.2.15 pe2 / r/ w port e i/o pin 2 pe2 is a general purpose input or output pin. in mcu expanded modes of operations, this pin drives the read/write output signal for the external bus. it indicates the direction of data on the external bus. 2.2.16 pe1 / irq port e input pin 1 pe1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. 2.2.17 pe0 / xirq port e input pin 0 pe0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. 2.2.18 ph7 / kwh7 port h i/o pin 7 ph7 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 2.2.19 ph6 / kwh6 port h i/o pin 6 ph6 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 2.2.20 ph5 / kwh5 port h i/o pin 5 ph5 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 2.2.21 ph4 / kwh4 port h i/o pin 2 ph4 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 2.2.22 ph3 / kwh3 port h i/o pin 3 ph3 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 56 2.2.23 ph2 / kwh2 port h i/o pin 2 ph2 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 2.2.24 ph1 / kwh1 port h i/o pin 1 ph1 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 2.2.25 ph0 / kwh0 port h i/o pin 0 ph0 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 2.2.26 pj7 / kwj7 / scl port j i/o pins 7 pj7 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as the serial clock pin scl of the iic module. 2.2.27 pj6 / kwj6 / sda port j i/o pins 6 pj6 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as the serial data pin sda of the iic module. 2.2.28 pj[1:0] / kwj[1:0] port j i/o pins [1:0] pj1 and pj0 are general purpose input or output pins. they can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 2.2.29 pk7 / ecs / romctl port k i/o pin 7 pk7 is a general purpose input or output pin. during mcu expanded modes of operation, this pin is used as the emulation chip select output ( ecs). while configurating mcu expanded modes this pin is used to enable the flash eeprom memory in the memory map (romctl). at the rising edge of reset, the state of this pin is latched to the romon bit. for a complete list of modes refer to 4.2 chip configuration summary . 2.2.30 pk[5:0] / xaddr[19:14] port k i/o pins [5:0] pk5-pk0 are general purpose input or output pins. in mcu expanded modes of operation, these pins provide the expanded address xaddr[19:14] for the external bus. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 57 2.2.31 pm7 port m i/o pin 7 pm7 is a general purpose input or output pin. 2.2.32 pm6 port m i/o pin 6 pm6 is a general purpose input or output pin. 2.2.33 pm5 / sck0 port m i/o pin 5 pm5 is a general purpose input or output pin. it can be configured as the serial clock pin sck of the serial peripheral interface 0 (spi0). 2.2.34 pm4 / mosi0 port m i/o pin 4 pm4 is a general purpose input or output pin. it can be configured as the master output (during master mode) or slave input pin (during slave mode) mosi for the serial peripheral interface 0 (spi0). 2.2.35 pm3 / ss0 port m i/o pin 3 pm3 is a general purpose input or output pin. it can be configured as the slave select pin ss of the serial peripheral interface 0 (spi0). 2.2.36 pm2 / miso0 port m i/o pin 2 pm2 is a general purpose input or output pin. it can be configured as the master input (during master mode) or slave output pin (during slave mode) miso for the serial peripheral interface 0 (spi0). 2.2.37 pm1 / txcan0 port m i/o pin 1 pm1 is a general purpose input or output pin. it can be configured as the transmit pin txcan of the motorola scalable controller area network controller 0 (can0). 2.2.38 pm0 / rxcan0 port m i/o pin 0 pm0 is a general purpose input or output pin. it can be configured as the receive pin rxcan of the motorola scalable controller area network controller 0 (can0). 2.2.39 pp7 / kwp7 / pwm7 port p i/o pin 7 pp7 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 7 output. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 58 2.2.40 pp6 / kwp6 / pwm6 port p i/o pin 6 pp6 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 6 output. 2.2.41 pp5 / kwp5 / pwm5 port p i/o pin 5 pp5 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 5 output. 2.2.42 pp4 / kwp4 / pwm4 port p i/o pin 4 pp4 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 4 output. 2.2.43 pp3 / kwp3 / pwm3 port p i/o pin 3 pp3 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 3 output. 2.2.44 pp2 / kwp2 / pwm2 port p i/o pin 2 pp2 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 2 output. 2.2.45 pp1 / kwp1 / pwm1 port p i/o pin 1 pp1 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 1 output. 2.2.46 pp0 / kwp0 / pwm0 port p i/o pin 0 pp0 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 0 output. 2.2.47 ps7 / ss0 port s i/o pin 7 ps6 is a general purpose input or output pin. it can be configured as the slave select pin ss of the serial peripheral interface 0 (spi0). 2.2.48 ps6 / sck0 port s i/o pin 6 ps6 is a general purpose input or output pin. it can be configured as the serial clock pin sck of the serial peripheral interface 0 (spi0). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 59 2.2.49 ps5 / mosi0 port s i/o pin 5 ps5 is a general purpose input or output pin. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 0 (spi0). 2.2.50 ps4 / miso0 port s i/o pin 4 ps4 is a general purpose input or output pin. it can be configured as master input (during master mode) or slave output pin (during slave mode) mosi of the serial peripheral interface 0 (spi0). 2.2.51 ps3 / txd1 port s i/o pin 3 ps3 is a general purpose input or output pin. it can be configured as the transmit pin txd of serial communication interface 1 (sci1). 2.2.52 ps2 / rxd1 port s i/o pin 2 ps2 is a general purpose input or output pin. it can be configured as the receive pin rxd of serial communication interface 1 (sci1). 2.2.53 ps1 / txd0 port s i/o pin 1 ps1 is a general purpose input or output pin. it can be configured as the transmit pin txd of serial communication interface 0 (sci0). 2.2.54 ps0 / rxd0 port s i/o pin 0 ps0 is a general purpose input or output pin. it can be configured as the receive pin rxd of serial communication interface 0 (sci0). 2.2.55 pt[7:0] / ioc[7:0] port t i/o pins [7:0] pt7-pt0 are general purpose input or output pins. they can be configured as input capture or output compare pins ioc7-ioc0 of the timer (tim). 2.3 power supply pins mc9s12b128 power and ground pins are described below. note: all vss pins must be connected together in the application. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 60 table 2-2 mc9s12b128 power and ground connection summary 2.3.1 vddx, vssx power & ground pins for i/o drivers external power and ground for i/o drivers. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily the mcu pins are loaded. vddx and vssx are the supplies for ports j, k, m, p, t and s. 2.3.2 vddr, vssr power & ground pins for i/o drivers & for internal voltage regulator external power and ground for i/o drivers and input to the internal voltage regulator. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily the mcu pins are loaded. vddr and vssr are the supplies for ports a, b, e and h. mnemonic pin number nominal voltage description 112-pin qfp vdd1, 2 13, 65 2.5v internal power and ground generated by internal regulator vss1, 2 14, 66 0v vddr 41 5.0v external power and ground, supply to pin drivers and internal voltage regulator. vssr 40 0v vddx 107 5.0v external power and ground, supply to pin drivers. vssx 106 0v vdda 83 5.0v operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the a/d to be bypassed independently. vssa 86 0v vrl 85 0v reference voltages for the analog-to-digital converter. vrh 84 5.0v vddpll 43 2.5v provides operating voltage and ground for the phased-locked loop. this allows the supply voltage to the pll to be bypassed independently. internal power and ground generated by internal regulator. vsspll 45 0v vregen 97 5.0v internal voltage regulator enable/disable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 61 2.3.3 vdd1, vdd2, vss1, vss2 internal logic power supply pins power is supplied to the mcu through vdd and vss. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. this 2.5v supply is derived from the internal voltage regulator. there is no static load on those pins allowed. the internal voltage regulator is turned off, if vregen is tied to ground. note: no load allowed except for bypass capacitors. 2.3.4 vdda, vssa power supply pins for atd and vreg vdda, vssa are the power supply and ground input pins for the voltage regulator and the two analog to digital converters. it also provides the reference for the internal voltage regulator. this allows the supply voltage to atd0/atd1 and the reference voltage to be bypassed independently. 2.3.5 vrh, vrl atd reference voltage input pins vrh and vrl are the reference voltage input pins for the analog to digital converter. 2.3.6 vddpll, vsspll power supply pins for pll provides operating voltage and ground for the oscillator and the phased-locked loop. this allows the supply voltage to the oscillator and pll to be bypassed independently.this 2.5v voltage is generated by the internal voltage regulator. note: no load allowed except for bypass capacitors. 2.3.7 vregen on chip voltage regulator enable enables the internal 5v to 2.5v voltage regulator. if this pin is tied low, vdd1,2 and vddpll must be supplied externally. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 62 section 3 system clock description the clock and reset generator provides the internal clock signals for the core and all peripheral modules. figure 3-1 shows the clock connections from the crg to all modules. consult the crg block user guide for details on clock generation. figure 3-1 clock connections osc bus clock core clock extal xtal oscillator clock hcs12_core ram sci0, sci1 pwm atd eeprom flash tim spi0 can0 pim int iic bkp mmc mebi bdm cpu crg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 63 section 4 modes of operation 4.1 overview eight possible modes determine the operating configuration of the mc9s12b128. each mode has an associated default memory map and external bus configuration. three low power modes exist for the device. 4.2 chip configuration summary the operating mode out of reset is determined by the states of the modc, modb, and moda pins during reset ( table 4-1 ). the modc, modb, and moda bits in the mode register show the current operating mode and provide limited mode switching during operation. the states of the modc, modb, and moda pins are latched into these bits on the rising edge of the reset signal. the romctl signal allows the setting of the romon bit in the misc register thus controlling whether the internal flash is visible in the memory map. romon = 1 mean the flash is visible in the memory map. the state of the romctl pin is latched into the romon bit in the misc register on the rising edge of the reset signal. for further explanation on the modes refer to the hcs12 multiplexed external bus interface block guide. table 4-1 mode selection bkgd = modc pe6 = modb pe5 = moda pk7 = romctl romon bit mode description 000x1 special single chip, bdm allowed and active. bdm is allowed in all other modes but a serial command is required to make bdm active. 001 01 emulation expanded narrow, bdm allowed 10 0 1 0 x 0 special test (expanded wide), bdm allowed 011 01 emulation expanded wide, bdm allowed 10 1 0 0 x 1 normal single chip, bdm allowed 101 00 normal expanded narrow, bdm allowed 11 110x1 peripheral; bdm allowed but bus operations would cause bus con?icts (must not be used) 111 00 normal expanded wide, bdm allowed 11 table 4-2 clock selection based on pe7 pe7 = xclks description 1 colpitts oscillator selected f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 64 4.3 security the device will make available a security feature preventing the unauthorized read and write of the memory contents. this feature allows: ? protection of the contents of flash, ? protection of the contents of eeprom, ? operation in single-chip mode, ? operation from external memory with internal flash and eeprom disabled. the user must be reminded that part of the security must lie with the users code. an extreme example would be users code that dumps the contents of the internal program. this code would defeat the purpose of security. at the same time the user may also wish to put a back door in the users program. an example of this is the user downloads a key through the sci which allows access to a programming routine that updates parameters stored in eeprom. 4.3.1 securing the microcontroller once the user has programmed the flash and eeprom (if desired), the part can be secured by programming the security bits located in the flash module. these non-volatile bits will keep the part secured through resetting the part and through powering down the part. the security byte resides in a portion of the flash array. check the flash block user guide for more details on the security configuration. 4.3.2 operation of the secured microcontroller 4.3.2.1 normal single chip mode this will be the most common usage of the secured part. everything will appear the same as if the part was not secured with the exception of bdm operation. the bdm operation will be blocked. 0 pierce oscillator/external clock selected table 4-3 voltage regulator vregen vregen description 1 internal voltage regulator enabled 0 internal voltage regulator disabled, vdd1,2 and vddpll must be supplied externally with 2.5v table 4-2 clock selection based on pe7 pe7 = xclks description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 65 4.3.2.2 executing from external memory the user may wish to execute from external space with a secured microcontroller. this is accomplished by resetting directly into expanded mode. the internal flash and eeprom will be disabled. bdm operations will be blocked. 4.3.3 unsecuring the microcontroller in order to unsecure the microcontroller, the internal flash and eeprom must be erased. this can be done through an external program in expanded mode or via a sequence of bdm commands. unsecuring is also possible via the backdoor key access. refer to flash block guide for details. once the user has erased the flash and eeprom, the part can be reset into special single chip mode. this invokes a program that verifies the erasure of the internal flash and eeprom. once this program completes, the user can erase and program the flash security bits to the unsecured state. this is generally done through the bdm, but the user could also change to expanded mode (by writing the mode bits through the bdm) and jumping to an external program (again through bdm commands). note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again. 4.4 low power modes the microcontroller features three main low power modes. consult the respective block user guide for information on the module behavior in stop, pseudo stop, and wait mode. an important source of information about the clock system is the clock and reset generator user guide (crg). 4.4.1 stop executing the cpu stop instruction stops all clocks and the oscillator thus putting the chip in fully static mode. wake up from this mode can be done via reset or external interrupts. 4.4.2 pseudo stop this mode is entered by executing the cpu stop instruction. in this mode the oscillator is still running and the real time interrupt (rti) or watchdog (cop) sub module can stay active. other peripherals are turned off. this mode consumes more current than the full stop mode, but the wake up time from this mode is significantly shorter. 4.4.3 wait this mode is entered by executing the cpu wai instruction. in this mode the cpu will not execute instructions. the internal cpu signals (address and databus) will be fully static. all peripherals stay active. for further power consumption the peripherals can individually turn off their local clocks. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 66 4.4.4 run although this is not a low power mode, unused peripheral modules should not be enabled in order to save power. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 67 section 5 resets and interrupts 5.1 overview consult the exception processing section of the cpu12 reference manual for information on resets and interrupts. 5.2 vectors 5.2.1 vector table table 5-1 lists interrupt sources and vectors in default order of priority. table 5-1 interrupt vector locations vector address interrupt source ccr mask local enable hprio value to elevate $fffe, $ffff external reset, power on reset or low voltage reset (see crg flags register to determine reset source) none none C $fffc, $fffd clock monitor fail reset none pllctl (cme, scme) C $fffa, $fffb cop failure reset none cop rate select C $fff8, $fff9 unimplemented instruction trap none none C $fff6, $fff7 swi none none C $fff4, $fff5 xirq x-bit none C $fff2, $fff3 irq i-bit irqcr (irqen) $f2 $fff0, $fff1 real time interrupt i-bit crgint (rtie) $f0 $ffee, $ffef standard timer channel 0 i-bit tie (c0i) $ee $ffec, $ffed standard timer channel 1 i-bit tie (c1i) $ec $ffea, $ffeb standard timer channel 2 i-bit tie (c2i) $ea $ffe8, $ffe9 standard timer channel 3 i-bit tie (c3i) $e8 $ffe6, $ffe7 standard timer channel 4 i-bit tie (c4i) $e6 $ffe4, $ffe5 standard timer channel 5 i-bit tie (c5i) $e4 $ffe2, $ffe3 standard timer channel 6 i-bit tie (c6i) $e2 $ffe0, $ffe1 standard timer channel 7 i-bit tie (c7i) $e0 $ffde, $ffdf standard timer over?ow i-bit tmsk2 (toi) $de $ffdc, $ffdd pulse accumulator a over?ow i-bit pactl (paovi) $dc $ffda, $ffdb pulse accumulator input edge i-bit pactl (pai) $da $ffd8, $ffd9 spi0 i-bit spicr1 (spie, sptie) $d8 $ffd6, $ffd7 sci0 i-bit scicr2 (tie, tcie, rie, ilie) $d6 $ffd4, $ffd5 sci1 i-bit scicr2 (tie, tcie, rie, ilie) $d4 $ffd2, $ffd3 atd i-bit atdctl2 (ascie) $d2 $ffd0, $ffd1 reserved i-bit reserved $d0 $ffce, $ffcf port j i-bit piej (piej7, piej6, piej1, piej0) $ce f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 68 5.3 resets when a reset occurs, mcu registers and control bits are changed to known start-up states. refer to the respective module block user guides for register reset states. for details on the different kind of resets refer to the hcs12 interrupt, crg and vreg_3v3 block user guides. $ffcc, $ffcd port h i-bit pieh (pieh7-0) $cc $ffca, $ffcb reserved i-bit reserved $ca $ffc8, $ffc9 i-bit $c8 $ffc6, $ffc7 crg pll lock i-bit crgint (lockie) $c6 $ffc4, $ffc5 crg self clock mode i-bit crgint (scmie) $c4 $ffc2, $ffc3 reserved i-bit reserved $c2 $ffc0, $ffc1 iic bus i-bit ibcr (ibie) $c0 $ffbe, $ffbf reserved i-bit reserved $be $ffbc, $ffbd i-bit $bc $ffba, $ffbb eeprom i-bit ecnfg (ccie, cbeie) $ba $ffb8, $ffb9 flash i-bit fcnfg (ccie, cbeie) $b8 $ffb6, $ffb7 can0 wake-up i-bit canrier (wupie) $b6 $ffb4, $ffb5 can0 errors i-bit canrier (cscie, ovrie) $b4 $ffb2, $ffb3 can0 receive i-bit canrier (rxfie) $b2 $ffb0, $ffb1 can0 transmit i-bit cantier (txeie2-txeie0) $b0 $ffae, $ffaf reserved i-bit reserved $ae $ffac, $ffad i-bit $ac $ffaa, $ffab i-bit $aa $ffa8, $ffa9 i-bit $a8 $ffa6, $ffa7 i-bit $a6 $ffa4, $ffa5 i-bit $a4 $ffa2, $ffa3 i-bit $a2 $ffa0, $ffa1 i-bit $a0 $ff9e, $ff9f i-bit $9e $ff9c, $ff9d i-bit $9c $ff9a, $ff9b i-bit $9a $ff98, $ff99 i-bit $98 $ff96, $ff97 i-bit $96 $ff94, $ff95 i-bit $94 $ff92, $ff93 i-bit $92 $ff90, $ff91 i-bit $90 $ff8e, $ff8f port p i-bit piep (piep7-0) $8e $ff8c, $ff8d pwm emergency shutdown i-bit pwmsdn (pwmie) $8c $ff8a, $ff8b vreg lvi i-bit ctrl0 (lvie) $8a $ff80 to $ff89 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 69 5.3.1 i/o pins refer to the hcs12 multiplexed external bus interface (mebi) block guide for mode dependent pin configuration of port a, b, e and k out of reset. refer to the pim block user guide for reset configurations of all peripheral module ports. note: for devices assembled in 80-pin qfp packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. refer to table 2-1 for affected pins. 5.3.2 memory refer to table 1-1 for locations of the memories depending on the operating mode after reset. the ram array is not automatically initialized out of reset. 5.4 interrupts for details on the different kind of interrupts refer to the hcs12 interrupt block user guide and according module block user guides. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 70 section 6 hcs12 core block description 6.1 cpu12 block description consult the cpu12 reference manual for information on the cpu. 6.1.1 device-specific information when the cpu12 reference manual refers to cycles this is equivalent to bus clock periods. so 1 cycle is equivalent to 1 bus clock period. 6.2 hcs12 module mapping control (mmc) block description consult the mmc block guide for information on the hcs12 module mapping control module. 6.2.1 device-specific information ? initee C reset state: $01 C bits ee11-ee15 are "write once in normal and emulation modes and write anytime in special modes". ? ppage C reset state: $00 C register is "write anytime in all modes" ? for memory size registers see table 1-4 . 6.3 hcs12 multiplexed external bus interface (mebi) block description consult the mebi block guide for information on hcs12 multiplexed external bus interface module. 6.3.1 device-specific information ? pucr C reset state: $90 6.4 hcs12 interrupt (int) block description consult the int block guide for information on the hcs12 interrupt module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 71 6.5 hcs12 background debug (bdm) block description consult the bdm block guide for information on the hcs12 background debug module. 6.5.1 device-specific information when the bdm block guide refers to alternate clock this is equivalent to oscillator clock. 6.6 hcs12 breakpoint (bkp) block description consult the bkp block guide for information on the hcs12 breakpoint module. section 7 voltage regulator (vreg3v3) block description consult the vreg3v3 block user guide for information about the dual output linear voltage regulator. vregen is accessible externally. section 8 clock and reset generator (crg) block description consult the crg block user guide for information about the clock and reset generator module. 8.1 device-specific information the low voltage reset feature of the crg is available on this device. note: if the voltage regulator is shut downed by connecting vregen to the corresponding ground pin then the lvrf flag in the crg flags register (crgflg) is undefined. section 9 oscillator (osc) block description consult the osc block user guide for information about the oscillator module. 9.1 device-specific information the xclks input signal is active low (see 2.2.10 pe7 / noacc / xclks port e i/o pin 7 ). section 10 standard timer (tim) block description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 72 consult the tim_16b8c block user guide for information about the standard timer module. when the tim_16b8c block user guide refers to freeze mode this is equivalent to active bdm mode . section 11 analog to digital converter (atd) block description consult the atd_10b16c block user guide for information about the analog to digital converter module. when the atd_10b16c block user guide refers to freeze mode this is equivalent to active bdm mode . the etrig pin option is not available, but the external trigger feature is available on atd channels. section 12 inter-ic bus (iic) block description consult the iic block user guide for information about the inter-ic bus module. section 13 serial communications interface (sci) block description there are two serial communications interfaces (sci1 and sci0) implemented on the mc9s12b128 device. consult the sci block user guide for information about each serial communications interface module. section 14 serial peripheral interface (spi) block description consult the spi block user guide for information about the serial peripheral interface module. section 15 flash eeprom 128k1 block description consult the fts128k1 block user guide for information about the flash module. the "s12 lrae" is a generic load ram and execute (lrae) program which will be programmed into the flash memory of this device during manufacture. this lrae program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using can or sci after it is assembled on the pcb. use of the lrae program is at the discretion of the end user and, if not required, it must simply be erased prior to flash programming. for more details of the s12 lrae and its implementation, please see the s12 lrea application note (an2546/d). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 73 section 16 eeprom 1k block description consult the eets1k block user guide for information about the eeprom module. section 17 ram block description this module supports single-cycle misaligned word accesses. section 18 mscan block description consult the mscan block user guide for information about the motorola scalable can module. section 19 pulse width modulator (pwm) block description consult the pwm_8b8c block user guide for information about the pulse width modulator module. when the pwm_8b8c block user guide refers to freeze mode this is equivalent to active bdm mode . section 20 port integration module (pim) block description consult the pim_9b128 block user guide for information about the port integration module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 74 section 21 printed circuit board layout proposals table 21-1 suggested external component values the pcb must be carefully laid out to ensure proper operation of the voltage regulator as well as of the mcu itself. the following rules must be observed: ? every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins(c1 - c6). ? central point of the ground star should be the vssr pin. ? use low ohmic low inductance connections between vss1, vss2 and vssr. ? vsspll must be directly connected to vssr. ? keep traces of vsspll, extal and xtal as short as possible and occupied board area for c7, c8, c11 and q1 as small as possible. ? do not place other signals or supplies underneath area occupied by c7, c8, c10 and q1 and the connection area to the mcu. ? central power input should be fed in at the vdda/vssa pins. component purpose type value c1 vdd1 ?lter cap ceramic x7r 100 .. 220nf c2 vdd2 ?lter cap ceramic x7r 100 .. 220nf c3 vdda ?lter cap ceramic x7r 100nf c4 vddr ?lter cap x7r/tantalum >=100nf c5 vddpll ?lter cap ceramic x7r 100nf c6 vddx ?lter cap x7r/tantalum >=100nf c7 osc load cap see pll speci?cation chapter c8 osc load cap c9 / c s pll loop ?lter cap see pll speci?cation chapter c10 / c p pll loop ?lter cap c11 / c dc dc cutoff cap colpitts mode only, if recommended by quartz manufacturer r1 pll loop ?lter res see pll speci?cation chapter r2 / r b osc res pierce mode only r3 / r s osc res q1 quartz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 75 figure 21-1 recommended pcb layout 112lqfp colpitts oscillator c5 c4 c1 c6 c3 c2 c8 c7 q1 c10 c9 r1 vddx vssx vddr vssr vdd1 vss1 vdd2 vss2 vddpll vsspll vdda vssa vregen c11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 76 figure 21-2 recommended pcb layout for 80qfp colpitts oscillator c5 c4 c3 c2 c8 c7 c10 c9 r1 c11 c6 c1 q1 vdd1 vss1 vss2 vdd2 vssr vddr vsspll vddpll vdda vssa vssx vregen vddx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 77 figure 21-3 recommended pcb layout for 112lqfp pierce oscillator c5 c4 c1 c6 c3 c2 c10 c9 r1 vddx vssx vddr vssr vdd1 vss1 vdd2 vss2 vddpll vsspll vdda vssa vregen r2 c7 r3 c8 q1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 78 figure 21-4 recommended pcb layout for 80qfp pierce oscillator c5 c4 c3 c2 c10 c9 r1 c6 c1 vdd1 vss1 vss2 vdd2 vssr vddr vsspll vddpll vdda vssa vssx vregen vddx r2 c7 r3 c8 q1 vsspll f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 79 appendix a electrical characteristics a.1 general note: the electrical characteristics given in this section are preliminary and should be used as a guide only. values cannot be guaranteed by motorola and are subject to change without notice. note: the part is specified and tested over the 5v and 3.3v ranges. for the intermediate range, generally the electrical specifications for the 3.3v range apply, but the part is not tested in production test in the intermediate range. this supplement contains the most accurate electrical information for the mc9s12b128 microcontroller available at the time of publication. the information should be considered preliminary and is subject to change. this introduction is intended to give an overview on several common topics like power supply, current injection etc. a.1.1 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. note: this classification is shown in the column labeled c in the parameter tables where appropriate. p: those parameters are guaranteed during production testing on each individual device. c: those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t: those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d: those parameters are derived mainly from simulations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 80 a.1.2 power supply the mc9s12b128 utilizes several pins to supply power to the i/o ports, a/d converter, oscillator, pll and internal logic. the vdda, vssa pair supplies the a/d converter and the internal voltage regulator. the vddx, vssx, vddr and vssr pairs supply the i/o pins, vddr supplies also the internal voltage regulator. vdd1, vss1, vdd2 and vss2 are the supply pins for the internal logic, vddpll, vsspll supply the oscillator and the pll. vss1 and vss2 are internally connected by metal. vdda, vddx, vddr as well as vssa, vssx, vssr are connected by anti-parallel diodes for esd protection. note: in the following context vdd5 is used for either vdda, vddr and vddx; vss5 is used for either vssa, vssr and vssx unless otherwise noted. idd5 denotes the sum of the currents flowing into the vdda, vddx and vddr pins. vdd is used for vdd1, vdd2 and vddpll, vss is used for vss1, vss2 and vsspll. idd is used for the sum of the currents flowing into vdd1 and vdd2. a.1.3 pins there are four groups of functional pins. a.1.3.1 5v i/o pins those i/o pins have a nominal level of 5v. this class of pins is comprised of all port i/o pins, the analog inputs, bkgd and the reset pins.the internal structure of all those pins is identical, however some of the functionality may be disabled. e.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. a.1.3.2 analog reference this group is made up by the vrh and vrl pins. a.1.3.3 oscillator the pins xfc, extal, xtal dedicated to the oscillator have a nominal 2.5v level. they are supplied by vddpll. a.1.3.4 test this pin is used for production testing only. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 81 a.1.3.5 vregen this pin is used to enable the on chip voltage regulator. a.1.4 current injection power supply must maintain regulation within operating v dd5 or v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in >v dd5 ) is greater than i dd5 , the injection current may flow out of vdd5 and could result in external power supply going out of regulation. ensure external vdd5 load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. a.1.5 absolute maximum ratings absolute maximum ratings are stress ratings only. a functional operation under or outside those maxima is not guaranteed. stress beyond those limits may affect the reliability or cause permanent damage of the device. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss5 or v dd5 ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 82 a.1.6 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model. a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. table a-1 absolute maximum ratings 1 notes : 1. beyond absolute maximum ratings device might be damaged. num rating symbol min max unit 1 i/o, regulator and analog supply voltage v dd5 -0.3 6.5 v 2 internal logic supply voltage 2 2. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. v dd -0.3 3.0 v 3 pll supply voltage 2 v ddpll -0.3 3.0 v 4 voltage difference vddx to vddr and vdda d vddx -0.3 0.3 v 5 voltage difference vssx to vssr and vssa d vssx -0.3 0.3 v 6 digital i/o input voltage v in -0.3 6.5 v 7 analog reference v rh, v rl -0.3 6.5 v 8 xfc, extal, xtal inputs v ilv -0.3 3.0 v 9 test input v test -0.3 10.0 v 10 instantaneous maximum current single pin limit for all digital i/o pins 3 3. all digital i/o pins are internally clamped to v ssx and v ddx , v ssr and v ddr or v ssa and v dda . i d -25 +25 ma 11 instantaneous maximum current single pin limit for xfc, extal, xtal 4 4. those pins are internally clamped to v sspll and v ddpll . i dl -25 +25 ma 12 instantaneous maximum current single pin limit for test 5 5. this pin is clamped low to v ssr , but not clamped high. this pin must be tied low in applications. i dt -0.25 0 ma 15 storage temperature range t stg C 65 155 c table a-2 esd and latch-up test conditions model description symbol value unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 83 a.1.7 operating conditions this chapter describes the operating conditions of the device. unless otherwise noted those conditions apply to all the following data. note: please refer to the temperature rating of the device (c, v, m) with regards to the ambient temperature t a and the junction temperature t j . for power dissipation calculations refer to section a.1.8 power dissipation and thermal characteristics . human body series resistance r1 1500 ohm storage capacitance c 100 pf number of pulse per pin positive negative - - 3 3 machine series resistance r1 0 ohm storage capacitance c 200 pf number of pulse per pin positive negative - - 3 3 latch-up minimum input voltage limit -2.5 v maximum input voltage limit 7.5 v table a-3 esd and latch-up protection characteristics num c rating symbol min max unit 1 t human body model (hbm) v hbm 2000 - v 2 t machine model (mm) v mm 200 - v 3 t charge device model (cdm) v cdm 500 - v 4t latch-up current at t a = 125 c positive negative i lat +100 -100 -ma 5t latch-up current at t a = 27 c positive negative i lat +200 -200 -ma table a-4 operating conditions rating symbol min typ max unit i/o, regulator and analog supply voltage v dd5 2.97 5 5.5 v internal logic supply voltage 1 v dd 2.35 2.5 2.75 v table a-2 esd and latch-up test conditions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 84 a.1.8 power dissipation and thermal characteristics power dissipation and thermal characteristics are closely related. the user must assure that the maximum operating junction temperature is not exceeded. the average chip-junction temperature (t j )in c can be obtained from: the total power dissipation can be calculated from: pll supply voltage 1 v ddpll 2.35 2.5 2.75 v voltage difference vddx to vddr and vdda d vddx -0.1 0 0.1 v voltage difference vssx to vssr and vssa d vssx -0.1 0 0.1 v oscillator f osc 0.5 - 16 mhz bus frequency f bus 0.25 2 - 25 3 mhz mc9s12b128 c operating junction temperature range t j -40 - 100 c operating ambient temperature range 4 t a -40 27 85 c mc9s12b128 v operating junction temperature range t j -40 - 120 c operating ambient temperature range 4 t a -40 27 105 c mc9s12b128 m operating junction temperature range t j -40 - 140 c operating ambient temperature range 4 t a -40 27 125 c notes : 1. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. this applies when this regulator is disabled and the device is powered from an external source. 2. some blocks e.g. atd (conversion) and nvms (program/erase) require higher bus frequencies for proper oper- ation. 3. see bus speed option at table 0-1 derivative differences 4. please refer to section a.1.8 power dissipation and thermal characteristics for more details about the rela- tion between ambient temperature t a and device junction temperature t j . table a-4 operating conditions t j t a p d q ja () + = t j junction temperature, [ c ] = t a ambient temperature, [ c ] = p d total chip power dissipation, [w] = q ja package thermal resistance, [ c/w] = p d p int p io + = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 85 two cases with internal voltage regulator enabled and disabled must be considered: 1. internal voltage regulator disabled p io is the sum of all output currents on i/o ports associated with vddx and vddr. for r dson is valid: respectively 2. internal voltage regulator enabled i ddr is the current shown in table a-8 and not the overall current flowing into vddr, which additionally contains the current flowing into the external loads with output high. p io is the sum of all output currents on i/o ports associated with vddx and vddr. p int chip internal power dissipation, [w] = p int i dd v dd i ddpll v ddpll i dda +v dda + = p io r dson i ? i io i 2 = r dson v ol i ol ------------ for outputs driven low ; = r dson v dd5 v oh C i oh ------------------------------------ for outputs driven high ; = p int i ddr v ddr i dda v dda + = p io r dson i ? i io i 2 = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 86 a.1.9 i/o characteristics this section describes the characteristics of all 5v i/o pins. all parameters are not always applicable, e.g. not all pins feature pull up/down resistances. table a-5 thermal package characteristics 1 notes : 1. the values for thermal resistance are achieved by package simulations num c rating symbol min typ max unit 1t thermal resistance lqfp112, single sided pcb 2 2. pc board according to eia/jedec standard 51-3 q ja CC54 o c/w 2t thermal resistance lqfp112, double sided pcb with 2 internal planes 3 3. pc board according to eia/jedec standard 51-7 q ja CC41 o c/w 3 t junction to board lqfp112 q jb CC31 o c/w 4 t junction to case lqfp112 q jc CC11 o c/w 5 t junction to package top lqfp112 y jt CC2 o c/w 6 t thermal resistance qfp 80, single sided pcb q ja CC51 o c/w 7t thermal resistance qfp 80, double sided pcb with 2 internal planes q ja CC41 o c/w 8 t junction to board qfp80 q jb CC27 o c/w 9 t junction to case qfp80 q jc CC14 o c/w 10 t junction to package top qfp80 y jt CC3 o c/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 87 table a-6 5v i/o characteristics conditions are 4.5< vddx <5.5v termperature from -40c to +140c, unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 - v dd5 + 0.3 v 2 p input low voltage v il v ss5 - 0.3 - 0.35*v dd5 v 3 c input hysteresis v hys 250 mv 4p input leakage current (pins in high impedance input mode) v in = v dd5 or v ss5 i in C1 - 1 m a 5p output high voltage (pins in output mode) partial drive i oh = C2ma full drive i oh = C10ma v oh v dd5 C 0.8 --v 6p output low voltage (pins in output mode) partial drive i ol = +2ma full drive i ol = +10ma v ol - - 0.8 v 7p internal pull up device current, tested at v il max. i pul - - C130 m a 8c internal pull up device current, tested at v ih min. i puh -10 - - m a 9p internal pull down device current, tested at v ih min. i pdh - - 130 m a 10 c internal pull down device current, tested at v il max. i pdl 10 - - m a 11 d input capacitance c in 7-pf 12 t injection current 1 single pin limit total device limit. sum of all injected currents notes : 1. refer to section a.1.4 current injection , for more details i ics i icp -2.5 -25 - 2.5 25 ma 13 p port h, j, p interrupt input pulse ?ltered 2 2. parameter only applies in stop or pseudo stop mode. t pign 3 m s 14 p port h, j, p interrupt input pulse passed 2 t pval 10 m s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 88 a.1.10 supply currents this section describes the current consumption characteristics of the device as well as the conditions for the measurements. table a-7 3.3v i/o characteristics conditions are vddx=3.3v +/-10% termperature from -40c to +140c, unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 - v dd5 + 0.3 v 2 p input low voltage v il v ss5 - 0.3 - 0.35*v dd5 v 3 c input hysteresis v hys 250 mv 4p input leakage current (pins in high impedance input mode) v in = v dd5 or v ss5 i in C1 - 1 m a 5p output high voltage (pins in output mode) partial drive i oh = C0.75ma full drive i oh = C4.5ma v oh v dd5 C 0.4 --v 6p output low voltage (pins in output mode) partial drive i ol = +0.9ma full drive i ol = +5.5ma v ol - - 0.4 v 7p internal pull up device current, tested at v il max. i pul - - C60 m a 8c internal pull up device current, tested at v ih min. i puh -6 - - m a 9p internal pull down device current, tested at v ih min. i pdh --60 m a 10 c internal pull down device current, tested at v il max. i pdl 6- - m a 11 d input capacitance c in 7-pf 12 t injection current 1 single pin limit total device limit. sum of all injected currents notes : 1. refer to section a.1.4 current injection , for more details i ics i icp -2.5 -25 - 2.5 25 ma 13 p port h, j, p interrupt input pulse ?ltered 2 2. parameter only applies in stop or pseudo stop mode. t pign 3 m s 14 p port h, j, p interrupt input pulse passed 2 t pval 10 m s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 89 a.1.10.1 measurement conditions all measurements are without output loads. unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25mhz or 16mhz bus frequency using a 4mhz oscillator in colpitts mode. production testing is performed using a square wave signal at the extal input. a.1.10.2 additional remarks in expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. no generally applicable numbers can be given. a very good estimate is to take the single chip currents and add the currents due to the external loads. table a-8 supply current characteristics at 25mhz bus frequency conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1p run supply currents single chip, internal regulator enabled i dd5 55 ma 2p p wait supply current all modules enabled, pll on only rti enabled 1 i ddw 35 7 ma 3 c p c c p c p c p pseudo stop current (rti and cop disabled) 1, 2 -40 c 27 c 70 c 85 c "c" temp option 100 c 105 c "v" temp option 120 c 125 c "m" temp option 140 c i ddps 370 400 450 550 600 650 800 850 1200 500 1600 2100 5000 m a 4 c c c c c c c pseudo stop current (rti and cop enabled) 1, 2 -40 c 27 c 70 c 85 c 105 c 125 c 140 c i ddps 570 600 650 750 850 1200 1500 m a 5 c p c c p c p c p stop current 2 -40 c 27 c 70 c 85 c "c" temp option 100 c 105 c "v" temp option 120 c 125 c "m" temp option 140 c i dds 12 25 100 130 160 200 350 400 600 100 1200 1700 5000 m a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 90 notes : 1. pll off 2. at those low power dissipation levels t j = t a can be assumed table a-9 supply current characteristics at 16mhz bus frequency conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1p run supply currents single chip, internal regulator enabled i dd5 55 ma 2p p wait supply current all modules enabled, pll on only rti enabled 1 i ddw 35 7 ma 3 c p c c p c p c p pseudo stop current (rti and cop disabled) 1, 2 -40 c 27 c 70 c 85 c "c" temp option 100 c 105 c "v" temp option 120 c 125 c "m" temp option 140 c notes : 1. pll off 2. at those low power dissipation levels t j = t a can be assumed i ddps 370 400 450 550 600 650 800 850 1200 500 1600 2100 5000 m a 4 c c c c c c c pseudo stop current (rti and cop enabled) 1, 2 -40 c 27 c 70 c 85 c 105 c 125 c 140 c i ddps 570 600 650 750 850 1200 1500 m a 5 c p c c p c p c p stop current 2 -40 c 27 c 70 c 85 c "c" temp option 100 c 105 c "v" temp option 120 c 125 c "m" temp option 140 c i dds 12 25 100 130 160 200 350 400 600 100 1200 1700 5000 m a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 91 a.2 atd characteristics this section describes the characteristics of the analog to digital converter. the atd is specified and tested for both the 3.3v and 5v range. for ranges between 3.3v and 5v the atd accuracy is generally the same as in the 3.3v range but is not tested in this range in production test. a.2.1 atd operating characteristics in 5v range the table a-10 shows conditions under which the atd operates. the following constraints exist to obtain full-scale, full range results: v ssa v rl v in v rh v dda . this constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. if the input level goes outside of this range it will effectively be clipped. a.2.2 atd operating characteristics in 3.3v range the table a-11 shows conditions under which the atd operates. the following constraints exist to obtain full-scale, full range results: v ssa v rl v in v rh v dda . this constraint exists since the sample buffer amplifier can not drive table a-10 atd operating characteristics in 5v range conditions are shown in table a-4 unless otherwise noted. supply voltage 5v-10% <= v dda <=5v+10% num c rating symbol min typ max unit 1d reference potential low high v rl v rh v ssa v dda /2 v dda /2 v dda v v 2c differential reference voltage 1 notes : 1. full accuracy is not guaranteed when differential voltage is less than 4.75v v rh -v rl 4.75 5.00 5.25 v 3 d atd clock frequency f atdclk 0.5 2.0 mhz 4d atd 10-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk 2. the minimum time assumes a final sample period of 2 atd clocks cycles while the maximum time assumes a final sample period of 16 atd clocks. n conv10 t conv10 14 7 28 14 cycles m s 5d atd 8-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk n conv8 t conv8 12 6 26 13 cycles m s 6d recovery time (v dda =5.0 volts) t rec 20 m s 7 p reference supply current i ref 0.750 ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 92 beyond the power supply levels that it ties to. if the input level goes outside of this range it will effectively be clipped. a.2.3 factors influencing accuracy three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the atd. a.2.3.1 source resistance: due to the input pin leakage current as specified in table a-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the atd input. the maximum source resistance r s specifies results in an error of less than 1/2 lsb (2.5mv) at the maximum leakage current. if device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. a.2.3.2 source capacitance when sampling an additional internal capacitor is switched to the input. this can cause a voltage drop due to charge sharing with the external and the pin capacitance. for a maximum sampling error of the input voltage 1lsb, then the external filter capacitor, c f 3 1024 * (c ins - c inn ). table a-11 atd operating characteristics in 3.3v range conditions are shown in table a-4 unless otherwise noted. supply voltage 3.3v-10% <= v dda <= 3.3v+10% num c rating symbol min typ max unit 1d reference potential low high v rl v rh v ssa v dda /2 v dda /2 v dda v v 2c differential reference voltage 1 notes : 1. full accuracy is not guaranteed when differential voltage is less than 3.0v v rh -v rl 3.0 3.3 3.6 v 3 d atd clock frequency f atdclk 0.5 2.0 mhz 4d atd 10-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk 2. the minimum time assumes a final sample period of 2 atd clocks cycles while the maximum time assumes a final sample period of 16 atd clocks. n conv10 t conv10 14 7 28 14 cycles m s 5d atd 8-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk n conv8 t conv8 12 6 26 13 cycles m s 6d recovery time (v dda =3.3 volts) t rec 20 m s 7 p reference supply current i ref 0.500 ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 93 a.2.3.3 current injection there are two cases to consider. 1. a current is injected into the channel being converted. the channel being stressed has conversion values of $3ff ($ff in 8-bit mode) for analog inputs greater than v rh and $000 for values less than v rl unless the current is higher than specified as disruptive condition. 2. current is injected into pins in the neighborhood of the channel being converted. a portion of this current is picked up by the channel (coupling ratio k), this additional current impacts the accuracy of the conversion depending on the source resistance. the additional input voltage error on the converted channel can be calculated as v err =k*r s * i inj , with i inj being the sum of the currents injected into the two pins adjacent to the converted channel. table a-12 atd electrical characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 c max input source resistance r s --1k w 2t total input capacitance non sampling sampling c inn c ins 10 22 pf 3 c disruptive analog input current i na -2.5 2.5 ma 4 c coupling ratio positive current injection k p 10 -4 a/a 5 c coupling ratio negative current injection k n 10 -2 a/a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 94 a.2.4 atd accuracy a.2.4.1 5v range table a-13 specifies the atd conversion performance excluding any errors due to current injection, input capacitance and source resistance. table a-13 atd conversion performance in 5v range conditions are shown in table a-4 unless otherwise noted v ref = v rh - v rl = 5.12v. resulting to one 8 bit count = 20mv and one 10 bit count = 5mv f atdclk = 2.0mhz supply voltage 5v-10% <= v dda <=5v+10% num c rating symbol min typ max unit 1 p 10-bit resolution lsb 5 mv 2 p 10-bit differential nonlinearity dnl C1 1 counts 3 p 10-bit integral nonlinearity inl C2.5 1.5 2.5 counts 4p 10-bit absolute error 1 notes : 1. these values include the quantization error which is inherently 1/2 count for any a/d converter. ae -3 2.0 3 counts 5 p 8-bit resolution lsb 20 mv 6 p 8-bit differential nonlinearity dnl C0.5 0.5 counts 7 p 8-bit integral nonlinearity inl C1.0 0.5 1.0 counts 8p 8-bit absolute error 1 ae -1.5 1.0 1.5 counts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 95 a.2.4.2 3.3v range table a-14 specifies the atd conversion performance excluding any errors due to current injection, input capacitance and source resistance. a.2.4.3 atd accuracy definitions for the following definitions see also figure a-1 . differential non-linearity (dnl) is defined as the difference between two adjacent switching steps. the integral non-linearity (inl) is defined as the sum of all dnls: table a-14 atd conversion performance in 3.3v range conditions are shown in table a-4 unless otherwise noted v ref = v rh - v rl = 3.328v. resulting to one 8 bit count = 13mv and one 10 bit count = 3.25mv f atdclk = 2.0mhz supply voltage 3.3v-10% <= v dda <= 3.3v+10% num c rating symbol min typ max unit 1 p 10-bit resolution lsb 3.25 mv 2 p 10-bit differential nonlinearity dnl C1.5 1.5 counts 3 p 10-bit integral nonlinearity inl C3.5 1.5 3.5 counts 4p 10-bit absolute error 1 notes : 1. these values include the quantization error which is inherently 1/2 count for any a/d converter. ae -5 2.5 5 counts 5 p 8-bit resolution lsb 13 mv 6 p 8-bit differential nonlinearity dnl C0.5 0.5 counts 7 p 8-bit integral nonlinearity inl C1.5 1.0 1.5 counts 8p 8-bit absolute error 1 ae -2.0 1.5 2.0 counts dnl i () v i v i1 C C 1lsb ------------------------ 1 C = inl n () dnl i () i1 = n ? v n v 0 C 1lsb ------------------- - n C == f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 96 figure a-1 atd accuracy definitions note: figure a-1 shows only definitions, for specification values refer to table a-13 . 1 5 vin mv 10 15 20 25 30 35 40 5085 5090 5095 5100 5105 5110 5115 5120 5065 5070 5075 5080 5060 0 3 2 5 4 7 6 45 $3f7 $3f9 $3f8 $3fb $3fa $3fd $3fc $3fe $3ff $3f4 $3f6 $3f5 8 9 1 2 $ff $fe $fd $3f3 10-bit resolution 8-bit resolution ideal transfer curve 10-bit transfer curve 8-bit transfer curve 5055 10-bit absolute error boundary 8-bit absolute error boundary lsb v i-1 v i dnl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 97 a.3 nvm, flash and eeprom note: unless otherwise noted the abbreviation nvm (non volatile memory) is used for both flash and eeprom. a.3.1 nvm timing the time base for all nvm program or erase operations is derived from the oscillator. a minimum oscillator frequency f nvmosc is required for performing program or erase operations. the nvm modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. attempting to program or erase the nvm modules at a lower frequency a full program or erase transition is not assured. the flash and eeprom program and erase operations are timed using a clock derived from the oscillator using the fclkdiv and eclkdiv registers respectively. the frequency of this clock must be set within the limits specified as f nvmop . the minimum program and erase times shown in table a-15 are calculated for maximum f nvmop and maximum f bus . the maximum times are calculated for minimum f nvmop and a f bus of 2mhz. a.3.1.1 single word programming the programming time for single word programming is dependant on the bus frequency as a well as on the frequency f nvmop and can be calculated according to the following formula. a.3.1.2 row programming this applies only to the flash where up to 64 words in a row can be programmed consecutively by keeping the command pipeline filled. the time to program a consecutive word can be calculated as: the time to program a whole row is: row programming is more than 2 times faster than single word programming. t swpgm 9 1 f nvmop --------------------- 25 1 f bus ---------- + = t bwpgm 4 1 f nvmop --------------------- 9 1 f bus ---------- + = t brpgm t swpgm 63 t bwpgm + = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 98 a.3.1.3 sector erase erasing a 1024 byte flash sector or a 4 byte eeprom sector takes: the setup time can be ignored for this operation. a.3.1.4 mass erase erasing a nvm block takes: the setup time can be ignored for this operation. a.3.1.5 blank check the time it takes to perform a blank check on the flash or eeprom is dependant on the location of the first non-blank word starting at relative address zero. it takes one bus cycle per word to verify plus a setup of the command. table a-15 nvm timing characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 d external oscillator clock f nvmosc 0.5 50 1 notes : 1. restrictions for oscillator in crystal mode apply! mhz 2 d bus frequency for programming or erase operations f nvmbus 1 mhz 3 d operating frequency f nvmop 150 200 khz 4 p single word programming time t swpgm 46 2 2. minimum programming times are achieved under maximum nvm operating frequency f nvmop and maximum bus frequency f bus . 74.5 3 m s 5d flash burst programming consecutive word 4 t bwpgm 20.4 2 31 3 m s 6d flash burst programming time for 64 words 4 t brpgm 1331.2 2 2027.5 3 m s 7 p sector erase time t era 20 5 26.7 3 ms 8 p mass erase time t mass 100 5 133 3 ms 9 d blank check time flash per block t check 11 6 65546 7 t cyc 10 d blank check time eeprom per block t check 11 6 522 7 t cyc t era 4000 1 f nvmop --------------------- ? t mass 20000 1 f nvmop --------------------- ? t check location t cyc 10 t cyc + ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 99 a.3.2 nvm reliability the reliability of the nvm blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. the failure rates for data retention and program/erase cycling are specified at the operating conditions noted. the program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. 3. maximum erase and programming times are achieved under particular combinations of f nvmop and bus frequency f bus . refer to formulae in sections a.3.1.1 - a.3.1.4 for guidance. 4. burst programming operations are not applicable to eeprom 5. minimum erase times are achieved under maximum nvm operating frequency f nvmop . 6. minimum time, if first word in the array is not blank 7. maximum time to complete check on an erased block table a-16 nvm reliability characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1c data retention at an average junction temperature of t javg = 70 c t nvmret 15 years 2 c flash number of program/erase cycles n flpe 10,000 cycles 3c eeprom number of program/erase cycles (C40 c t j 0 c) n eepe 10,000 cycles 4c eeprom number of program/erase cycles (0 c < t j 140 c) n eepe 100,000 cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 100 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 101 a.4 vreg_3v3 a.4.1 operating conditions a.4.2 chip power-up and voltage drops vreg_3v3 sub modules lvi (low voltage interrupt), por (power-on reset) and lvr (low voltage reset) handle chip power-up or drops of the supply voltage. their function is described in figure a-2 . table a-17 vreg_3v3 - operating conditions conditions are shown in table a-4 unless otherwise noted num c characteristic symbol min typical max unit 1 p input voltages v vddr,a 2.97 5.5 v 2p regulator current reduced power mode shutdown mode i reg 20 12 50 40 m a m a 3p output voltage core full performance mode reduced power mode shutdown mode v dd 2.35 1.6 2.5 2.5 1 notes : 1. high impedance output 2.75 2.75 v v v 4p output voltage pll full performance mode reduced power mode 2 reduced power mode 3 shutdown mode 2. current iddpll = 1ma (colpitts oscillator) 3. current iddpll = 3ma (pierce oscillator) v ddpll 2.35 2.0 1.6 2.5 2.5 2.5 4 4. high impedance output 2.75 2.75 2.75 v v v 7p low voltage interrupt 5 assert level deassert level 5. monitors v dda , active only in full performance mode. indicates i/o & adc performance degradation due to low supply voltage. v lvia v lvid 4.1 4.25 4.37 4.52 4.66 4.77 v v 8p low voltage reset 6 assert level 6. monitors v dd , active only in full performance mode. mcu is monitored by the por in rpm (see figure a-2 ) v lvra 2.25 v 9c power-on reset 7 assert level deassert level 7. monitors v dd . active in all modes. v pora v pord 0.97 2.05 v v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 102 figure a-2 vreg_3v3 - chip power-up and voltage drops (not scaled) a.4.3 output loads a.4.3.1 resistive loads on-chip voltage regulator vreg_3v3 intended to supply the internal logic and oscillator circuits allows no external dc loads. a.4.3.2 capacitive loads the capacitive loads are specified in table a-18 . ceramic capacitors with x7r dielectricum are required. v lvid v lvia v lvrd v lvra v pord lvi por lvr t v v dda v dd lvi enabled lvi disabled due to lvr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 103 table a-18 vreg_3v3 - capacitive loads num characteristic symbol min typical max unit 1 vdd external capacitive load c ddext 200 440 12000 nf 3 vddpll external capacitive load c ddpllext 90 220 5000 nf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 104 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 105 a.5 reset, oscillator and pll this section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked-loop (pll). a.5.1 startup table a-19 summarizes several startup characteristics explained in this section. detailed description of the startup behavior can be found in the clock and reset generator (crg) block user guide. table a-19 startup characteristics a.5.1.1 por the release level v pord (see table a-17 ) and the assert level v pora (see table a-17 ) are derived from the v dd supply. they are also valid if the device is powered externally. after releasing the por reset the oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is detected, the mcu will start using the internal self clock. the fastest startup time possible is given by n uposc . a.5.1.2 lvr the assert level v lvra (see table a-17 ) is derived from the v dd supply. after releasing the lvr reset the oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is detected, the mcu will start using the internal self clock. the fastest startup time possible is given by n uposc . a.5.1.3 sram data retention provided an appropriate external reset signal is applied to the mcu, preventing the cpu from executing code when vdd5 is out of specification limits, the sram contents integrity is guaranteed if after the reset the porf bit in the crg flags register has not been set. a.5.1.4 external reset when external reset is asserted for a time greater than pw rstl the crg module generates an internal reset, and the cpu starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 d reset input pulse width, minimum input time pw rstl 2 t osc 2 d startup from reset n rst 192 196 n osc 3 d interrupt pulse width, irq edge-sensitive mode pw irq 20 ns 4 d wait recovery startup time t wrs 14 t cyc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 106 a.5.1.5 stop recovery out of stop the controller can be woken up by an external interrupt. a clock quality check as after por is performed before releasing the clocks to the system. a.5.1.6 pseudo stop and wait recovery the recovery from pseudo stop and wait are essentially the same since the oscillator was not stopped in both modes. the controller can be woken up by internal or external interrupts. after t wrs the cpu starts fetching the interrupt vector. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 107 a.5.2 oscillator the device features an internal colpitts and pierce oscillator. the selection of colpitts oscillator or pierce oscillator/external clock depends on the xclks signal which is sampled during reset. pierce oscillator/external clock mode allows the input of a square wave. before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, stop or oscillator fail. t cqout specifies the maximum time before switching to the internal self clock mode after por or stop if a proper oscillation is not detected. the quality check also determines the minimum oscillator start-up time t uposc . the device also features a clock monitor. a clock monitor failure is asserted if the frequency of the incoming clock signal is below the assert frequency f cmfa . table a-20 oscillator characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1a c crystal oscillator range (colpitts) f osc 0.5 16 mhz 1b c crystal oscillator range (pierce) 1 notes : 1. depending on the crystal a damping series resistor might be necessary f osc 0.5 40 mhz 2 p startup current i osc 100 m a 3 c oscillator start-up time (colpitts) t uposc 8 2 2. f osc = 4mhz, c = 22pf. 100 3 3. maximum value is for extreme cases using high q, low frequency crystals ms 4 d clock quality check time-out t cqout 0.45 2.5 s 5 p clock monitor failure assert frequency f cmfa 50 100 200 khz 6p external square wave input frequency 4 4. only valid if pierce oscillator/external clock mode is selected f ext 0.5 50 mhz 7d external square wave pulse width low 4 t extl 9.5 ns 8d external square wave pulse width high 4 t exth 9.5 ns 9d external square wave rise time 4 t extr 1ns 10 d external square wave fall time 4 t extf 1ns 11 d input capacitance (extal, xtal pins) c in 7pf 12 c dc operating bias in colpitts con?guration on extal pin v dcbias 1.1 v 13 p extal pin input high voltage 4 v ih,extal 0.7*v ddpll v t extal pin input high voltage 4 v ih,extal v ddpll + 0.3 v 14 p extal pin input low voltage 4 v il,extal 0.3*v ddpll v t extal pin input low voltage 4 v il,extal v sspll - 0.3 v 15 c extal pin input hysteresis 4 v hys,extal 250 mv f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 108 a.5.3 phase locked loop the oscillator provides the reference clock for the pll. the plls voltage controlled oscillator (vco) is also the system clock source in self clock mode. a.5.3.1 xfc component selection this section describes the selection of the xfc components to achieve a good filter characteristics. figure a-3 basic pll functional diagram the following procedure can be used to calculate the resistance and capacitance values using typical values for k 1 , f 1 and i ch from table a-21 . the grey boxes show the calculation for f vco = 50mhz and f ref = 1mhz. e.g., these frequencies are used for f osc = 4mhz and a 25mhz bus clock. the vco gain at the desired vco frequency is approximated by: the phase detector relationship is given by: i ch is the current in tracking mode. f osc 1 refdv+1 f ref phase detector vco k v 1 synr+1 f vco loop divider k f 1 2 d f cmp c s r c p vddpll xfc pin k v k 1 e f 1 f vco C () k 1 1v ----------------------- = 100 C e 60 50 C () 100 C ----------------------- - = = -90.48mhz/v k f i ch C k v = = 316.7hz/ w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 109 the loop bandwidth f c should be chosen to fulfill the gardners stability criteria by at least a factor of 10, typical values are 50. z = 0.9 ensures a good transient response. and finally the frequency relationship is defined as with the above values the resistance can be calculated. the example is shown for a loop bandwidth f c =10khz: the capacitance c s can now be calculated as: the capacitance c p should be chosen in the range of: a.5.3.2 jitter information the basic functionality of the pll is shown in figure a-3 . with each transition of the clock f cmp , the deviation from the reference clock f ref is measured and input voltage to the vco is adjusted accordingly.the adjustment is done continuously with no abrupt changes in the clock output frequency. noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. this jitter affects the real minimum and maximum clock periods as illustrated in figure a-4 . f c 2 z f ref pz 1 z 2 + + ? ?? ------------------------------------------ 1 10 ------ f c f ref 410 -------------- z 0.9 = () ; < ? < f c < 25khz n f vco f ref ------------- 2 synr 1 + () == = 50 r 2 p nf c k f ---------------------------- - = =2* p *50*10khz/(316.7hz/ w ) =9.9k w =~10k w c s 2 z 2 p f c r --------------------- - 0.516 f c r -------------- - z 0.9 = () ; ? = = 5.19nf =~ 4.7nf c s 20 c p c s 10 c p = 470pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 110 figure a-4 jitter definitions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n). defining the jitter as: for n < 100, the following equation is a good fit for the maximum jitter: figure a-5 maximum bus clock jitter approximation 2 3 n-1 n 1 0 t nom t max1 t min1 t maxn t minn jn () max 1 t max n () nt nom --------------------- C 1 t min n () nt nom -------------------- - C , ? ? ?? = j n () j 1 n -------- j 2 + = 1 5 10 20 n j (n) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 111 this is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. table a-21 pll characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p self clock mode frequency f scm 1 5.5 mhz 2 d vco locking range f vco 8 50 mhz 3d lock detector transition from acquisition to tracking mode |d trk | 34 % 1 notes : 1. % deviation from target frequency 4 d lock detection |d lock | 0 1.5 % (1) 5 d un-lock detection |d unl | 0.5 2.5 % (1) 6d lock detector transition from tracking to acquisition mode |d unt | 68 % (1) 7c pllon total stabilization delay (auto mode) 2 2. f osc = 4mhz, f bus = 25mhz equivalent f vco = 50mhz: refdv = #$03, synr = #$018, cs = 4.7nf, cp = 470pf, rs = 10k w . t stab 0.5 ms 8d pllon acquisition mode stabilization delay (2) t acq 0.3 ms 9d pllon tracking mode stabilization delay (2) t al 0.2 ms 10 d fitting parameter vco loop gain k 1 -100 mhz/v 11 d fitting parameter vco loop frequency f 1 60 mhz 12 d charge pump current acquisition mode | i ch | 38.5 m a 13 d charge pump current tracking mode | i ch | 3.5 m a 14 c jitter ?t parameter 1 (2) j 1 1.1 % 15 c jitter ?t parameter 2 (2) j 2 0.13 % f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 112 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 113 a.6 mscan table a-22 mscan wake-up pulse characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p mscan wake-up dominant pulse ?ltered t wup 2 m s 2 p mscan wake-up dominant pulse pass t wup 5 m s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 114 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 115 a.7 spi this section provides electrical parametrics and ratings for the spi. in table a-23 the measurement conditions are listed. a.7.1 master mode in figure a-6 the timing diagram for master mode with transmission format cpha=0 is depicted. figure a-6 spi master timing (cpha=0) in figure a-7 the timing diagram for master mode with transmission format cpha=1 is depicted. table a-23 measurement conditions description value unit drive mode full drive mode load capacitance c load, on all outputs 50 pf thresholds for delay measurement points (20% / 80%) vddx v sck (output) sck (output) miso (input) mosi (output) ss 1 (output) 1 9 5 6 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 11 4 4 2 10 (cpol = 0) (cpol = 1) 3 13 13 1.if configured as an output. 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 12 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 116 figure a-7 spi master timing (cpha=1) in table a-24 the timing characteristics for master mode are listed. table a-24 spi master mode timing characteristics num characteristic symbol unit min typ max 1 sck frequency f sck 1/2048 1 / 2 f bus 1 sck period t sck 2 2048 t bus 2 enable lead time t lead 1/2 t sck 3 enable lag time t lag 1/2 t sck 4 clock (sck) high or low time t wsck 1/2 t sck 5 data setup time (inputs) t su 8 ns 6 data hold time (inputs) t hi 8 ns 9 data valid after sck edge t vsck 30 ns 10 data valid after ss fall (cpha=0) t vss 15 ns 11 data hold time (outputs) t ho 20 ns 12 rise and fall time inputs t r? 8 ns 13 rise and fall time outputs t rfo 8 ns sck (output) sck (output) miso (input) mosi (output) 1 5 6 msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 4 4 9 12 13 11 port data (cpol = 0) (cpol = 1) port data ss 1 (output) 2 12 13 3 1.if configured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 117 a.7.2 slave mode in figure a-8 the timing diagram for slave mode with transmission format cpha=0 is depicted. figure a-8 spi slave timing (cpha=0) in figure a-9 the timing diagram for slave mode with transmission format cpha=1 is depicted. sck (input) sck (input) mosi (input) miso (output) ss (input) 1 9 5 6 msb in bit 6 . . . 1 lsb in slave msb slave lsb out bit 6 . . . 1 11 4 4 2 7 (cpol = 0) (cpol = 1) 3 13 note: not defined! 12 12 11 see 13 note 8 10 see note f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 118 figure a-9 spi slave timing (cpha=1) in table a-25 the timing characteristics for slave mode are listed. table a-25 spi slave mode timing characteristics num characteristic symbol unit min typ max 1 sck frequency f sck dc 1 / 4 f bus 1 sck period t sck 4 t bus 2 enable lead time t lead 4 t bus 3 enable lag time t lag 4 t bus 4 clock (sck) high or low time t wsck 4 t bus 5 data setup time (inputs) t su 8 ns 6 data hold time (inputs) t hi 8 ns 7 slave access time (time to data active) t a 20 ns 8 slave miso disable time t dis 22 ns 9 data valid after sck edge t vsck 30 + t bus 1 notes : 1. t bus added due to internal synchronization delay ns 10 data valid after ss fall t vss 30 + t bus 1 ns 11 data hold time (outputs) t ho 20 ns 12 rise and fall time inputs t r? 8 ns 13 rise and fall time outputs t rfo 8 ns sck (input) sck (input) mosi (input) miso (output) 1 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 9 12 13 11 (cpol = 0) (cpol = 1) ss (input) 2 12 13 3 note: not defined! slave 7 8 see note f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 119 a.8 external bus timing a timing diagram of the external multiplexed-bus is illustrated in figure a-10 with the actual timing values shown on table a-26 in 5v range. all major bus signals are included in the diagram. while both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. a.8.1 general muxed bus timing the expanded bus timings are highly dependent on the load conditions. the timing parameters shown assume a balanced load across all outputs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 120 figure a-10 general external bus timing addr/data (read) addr/data (write) addr data data 5 10 11 8 16 6 eclk 1, 2 3 4 addr data data 12 15 9 7 14 13 ecs 21 20 22 23 non-multiplexed 17 19 lstrb 29 no a cc 32 ipipo0 ipipo1, pe6,5 35 18 27 28 30 33 36 31 34 r/ w 24 26 25 addresses pe4 pa, pb pa, pb pk5:0 pk7 pe2 pe3 pe7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 121 table a-26 expanded bus timing characteristics in 5v range conditions are shown in table a-4 unless otherwise noted, c load = 50pf. supply voltage 5v-10% <= v ddx <=5v+10% num c rating symbol min typ max unit 1 p frequency of operation (e-clock) f o 0 25.0 mhz 2 p cycle time t cyc 40 ns 3 d pulse width, e low pw el 19 ns 4d pulse width, e high 1 pw eh 19 ns 5 d address delay time t ad 8ns 6d address valid time to e rise (pw el Ct ad )t av 11 ns 7 d muxed address hold time t mah 2ns 8 d address hold to data valid t ahds 7ns 9 d data hold to address t dha 2ns 10 d read data setup time t dsr 13 ns 11 d read data hold time t dhr 0ns 12 d write data delay time t ddw 7ns 13 d write data hold time t dhw 2ns 14 d write data setup time 1 (pw eh Ct ddw ) t dsw 12 ns 15 d address access time 1 (t cyc Ct ad Ct dsr ) t acca 19 ns 16 d e high access time 1 (pw eh Ct dsr ) t acce 6ns 20 d chip select delay time t csd 16 ns 21 d chip select access time 1 (t cyc Ct csd Ct dsr ) t accs 11 ns 22 d chip select hold time t csh 2ns 23 d chip select negated time t csn 8ns 24 d read/write delay time t rwd 7ns 25 d read/write valid time to e rise (pw el Ct rwd )t rwv 14 ns 26 d read/write hold time t rwh 2ns 27 d low strobe delay time t lsd 7ns 28 d low strobe valid time to e rise (pw el Ct lsd )t lsv 14 ns 29 d low strobe hold time t lsh 2ns 30 d noacc strobe delay time t nod 7ns 31 d noacc valid time to e rise (pw el Ct nod )t nov 14 ns 32 d noacc hold time t noh 2ns 33 d ipipo[1:0] delay time t p0d 27ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 122 34 d ipipo[1:0] valid time to e rise (pw el Ct p0d )t p0v 11 ns 35 d ipipo[1:0] delay time 1 (pw eh -t p1v ) t p1d 225ns 36 d ipipo[1:0] valid time to e fall t p1v 11 ns notes : 1. affected by clock stretch: add n x t cyc where n=0,1,2 or 3, depending on the number of clock stretches. table a-26 expanded bus timing characteristics in 5v range conditions are shown in table a-4 unless otherwise noted, c load = 50pf. supply voltage 5v-10% <= v ddx <=5v+10% num c rating symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 123 appendix b package information b.1 general this section provides the physical dimensions of the mc9s12b128 packages. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 124 b.2 112-pin lqfp package figure b-1 112-pin lqfp mechanical dimensions (case no. 987) dim a min max 20.000 bsc millimeters a1 10.000 bsc b 20.000 bsc b1 10.000 bsc c --- 1.600 c1 0.050 0.150 c2 1.350 1.450 d 0.270 0.370 e 0.450 0.750 f 0.270 0.330 g 0.650 bsc j 0.090 0.170 k 0.500 ref p 0.325 bsc r1 0.100 0.200 r2 0.100 0.200 s 22.000 bsc s1 11.000 bsc v 22.000 bsc v1 11.000 bsc y 0.250 ref z 1.000 ref aa 0.090 0.160 q q q q 11 11 13 7 13 view y l-m 0.20 n t 4x 4x 28 tips pin 1 ident 1 112 85 84 28 57 29 56 b v v1 b1 a1 s1 a s view ab 0.10 3 c c2 q 2 q 0.050 seating plane gage plane 1 q q view ab c1 (z) (y) e (k) r2 r1 0.25 j1 view y j1 p g 108x 4x section j1-j1 base rotated 90 counterclockwise metal j aa f d l-m m 0.13 n t 1 2 3 c l l-m 0.20 n t l n m t t 112x x x=l, m or n r r notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.46. 8 3 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 125 b.3 80-pin qfp package figure b-2 80-pin qfp mechanical dimensions (case no. 841b) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, -b- and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. section b-b 61 60 detail a l 41 40 80 -a- l -d- a s a-b m 0.20 d s h 0.05 a-b s 120 21 -b- b v j f n d view rotated 90 detail a b b p -a-,-b-,-d- e h g m m detail c seating plane -c- c datum plane 0.10 -h- datum plane -h- u t r q k w x detail c dim min max millimeters a 13.90 14.10 b 13.90 14.10 c 2.15 2.45 d 0.22 0.38 e 2.00 2.40 f 0.22 0.33 g 0.65 bsc h --- 0.25 j 0.13 0.23 k 0.65 0.95 l 12.35 ref m 510 n 0.13 0.17 p 0.325 bsc q 07 r 0.13 0.30 s 16.95 17.45 t 0.13 --- u 0 --- v 16.95 17.45 w 0.35 0.45 x 1.6 ref s a-b m 0.20 d s c s a-b m 0.20 d s h 0.05 d s a-b m 0.20 d s c s a-b m 0.20 d s c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 126 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 127 device user guide end sheet f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . device user guide 9S12B128DGV1/d v01.10 128 final page of 128 pages f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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